公开(公告)号：US20180151719A1

公开(公告)日：2018-05-31

申请号：US15812430

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUNEICHIRO SANO ,  ATSUSHI OHOKA ,  TSUTOMU KIYOSAWA ,  OSAMU ISHIYAMA ,  TAKAYUKI WAKAYAMA ,  KOUICHI SAITOU ,  TAKASHI HASEGAWA ,  DAISUKE SHINDO ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L23/31 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L23/3192 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42356

Abstract: A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film. The first protective film covers the inner-circumferential upper source electrode, the upper gate electrode, and an inner side surface of the one or more outer-circumferential upper source electrodes except for a pad region. The second protective film covers the first protective film and at least a part of the one or more second conductivity type rings.

公开(公告)号：US20180254339A1

公开(公告)日：2018-09-06

申请号：US15896490

申请日：2018-02-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7805 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7828 ,  H01L2924/13091

Abstract: A semiconductor epitaxial wafer includes a semiconductor wafer, and a semiconductor layer of a first conductivity type disposed on a main surface of the semiconductor wafer. The semiconductor epitaxial wafer includes a plurality of device regions. The plurality of device regions each include a body region of a second conductivity type in contact with the semiconductor layer, a source region of the first conductivity type in contact with the body region, and a channel layer that is constituted by a semiconductor, and that is disposed on the semiconductor layer so as to be in contact with at least a part of the body region. In a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the first conductivity type impurity in the channel layer are negatively correlated to each other.

公开(公告)号：US20200303506A1

公开(公告)日：2020-09-24

申请号：US16776477

申请日：2020-01-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA ,  ATSUSHI OHOKA

IPC: H01L29/36 ,  H01L21/02 ,  H01L29/16 ,  H01L27/088 ,  H01L29/78

Abstract: Variations in device characteristics in a plane parallel to the principal surface of a semiconductor wafer are suppressed. A semiconductor epitaxial wafer includes a semiconductor wafer and a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer and contains a first conductivity type impurity, and the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer have a positive correlation in a plane parallel to the principal surface of the semiconductor wafer.

公开(公告)号：US20180277453A1

公开(公告)日：2018-09-27

申请号：US15911231

申请日：2018-03-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA

IPC: H01L21/66 ,  H01L29/78 ,  H01L21/82 ,  H01L21/8252 ,  H01L23/522

CPC classification number: H01L22/22 ,  H01L21/8213 ,  H01L21/8252 ,  H01L23/5226 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7827

Abstract: Semiconductor layer 110 is formed on semiconductor substrate 101. Semiconductor layer 110 has a plurality of well regions 103 in a surface remote from semiconductor substrate 101. Semiconductor layer 110 includes drift region 102 in addition to the plurality of well regions 103. The plurality of well regions 103 each include body region 105, source region 108, and contact region 109. Source region 108 is in contact with body region 105. Contact region 109 is in contact with both body region 105 and source region 108. Body region 105, source region 108, and source wire 118 are at an identical potential because of contact region 109. Semiconductor layer 110 includes ineffective region R at the surface remote from semiconductor substrate 101.

公开(公告)号：US20190245039A1

公开(公告)日：2019-08-08

申请号：US16254881

申请日：2019-01-23

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A silicon carbide semiconductor element includes a silicon carbide semiconductor layer of a first conductivity type, a body region of a second conductivity type, a channel layer made of a silicon carbide semiconductor disposed on the silicon carbide semiconductor layer so as to be in contact with at least a part of the body region, and a gate electrode disposed on the channel layer via a gate insulating film. The channel layer has a multilayer structure of a high-concentration impurity layer containing impurities of the first conductivity type, a first medium-concentration impurity layer containing impurities of the first conductivity type, and a first low-concentration impurity layer containing impurities of the first conductivity type. The first low-concentration impurity layer is disposed closer to the body region than the high-concentration impurity layer and the first medium-concentration impurity layer.

公开(公告)号：US20180277636A1

公开(公告)日：2018-09-27

申请号：US15911236

申请日：2018-03-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA ,  ATSUSHI OHOKA

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/32 ,  H01L29/872 ,  H01L29/08 ,  H01L29/78 ,  H01L21/66 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L22/12 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/872

Abstract: Semiconductor device 101 includes semiconductor substrate 10, drift layer 20, first electrode 50, and second electrode 60. Semiconductor substrate 10 is of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like. For example, semiconductor substrate 10 is an n-type silicon carbide semiconductor substrate. Drift layer 20 is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface 10a of semiconductor substrate 10 by epitaxial growth. Drift layer 20 is formed of for example, an n-type silicon carbide semiconductor. Drift layer 20 has a thickness of t. For example, the thickness t is between about 5 μm and about 100 μm (inclusive).

公开(公告)号：US20170170288A1

公开(公告)日：2017-06-15

申请号：US15434022

申请日：2017-02-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA ,  YASUYUKI YANASE ,  KAZUHIRO KAGAWA

IPC: H01L29/423 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/10

CPC classification number: H01L29/4236 ,  H01L21/0485 ,  H01L21/049 ,  H01L21/205 ,  H01L21/3247 ,  H01L23/544 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A semiconductor device includes a substrate having a main surface inclined in an off-direction from a {0001} surface, a semiconductor layer, and an epitaxial layer. The semiconductor layer includes a trench. Where an upstream side is an off-angle upstream side and a downstream side is an off-angle downstream side in a direction with the off-direction projected on the main surface of the substrate, a side wall of the trench includes first and second side wall portions facing each other and each crossing the off-direction of the substrate. The first side wall portion is situated closer to the off-angle upstream side than the second side wall portion.