公开(公告)号：US20180061980A1

公开(公告)日：2018-03-01

申请号：US15667895

申请日：2017-08-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/26 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7815 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/823481 ,  H01L27/085 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/26 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7811

Abstract: A semiconductor device including a main region, a sense region, a separation region electrically isolating the main and sense region regions includes a first semiconductor layer positioned on the main surface of a semiconductor substrate, a plurality of main cells disposed in the main region, and a plurality of sense cells disposed in the sense region. Source regions of the main cell become conductive with a source electrode and source regions of the sense cell become conductive with a sense electrode. The separation region includes a plurality of second conductivity type separation body regions and a barrier region and is disposed within a first semiconductor layer and is disposed to abut on the surface of the first semiconductor layer.

公开(公告)号：US20170077087A1

公开(公告)日：2017-03-16

申请号：US15342023

申请日：2016-11-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： NOBUYUKI HORIKAWA ,  OSAMU KUSUMOTO ,  MASASHI HAYASHI ,  MASAO UCHIDA

IPC: H01L27/06 ,  H01L29/41 ,  H01L29/868 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0605 ,  H01L27/04 ,  H01L27/0727 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/41 ,  H01L29/78 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

Abstract translation: 碳化硅半导体器件包括晶体管区域，二极管区域，栅极线区域和栅极焊盘区域。 栅极区域和栅极线区域分别被设置为夹在二极管区域和二极管区域之间，并且栅极区域上的栅极电极和栅极线区域形成在形成在外延层上的绝缘膜上。 因此，能够防止栅极绝缘膜在开关和雪崩击穿时的栅极区域的绝缘膜的破坏，而不会导致栅极绝缘膜的质量劣化。

公开(公告)号：US20180151719A1

公开(公告)日：2018-05-31

申请号：US15812430

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUNEICHIRO SANO ,  ATSUSHI OHOKA ,  TSUTOMU KIYOSAWA ,  OSAMU ISHIYAMA ,  TAKAYUKI WAKAYAMA ,  KOUICHI SAITOU ,  TAKASHI HASEGAWA ,  DAISUKE SHINDO ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L23/31 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L23/3192 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42356

Abstract: A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film. The first protective film covers the inner-circumferential upper source electrode, the upper gate electrode, and an inner side surface of the one or more outer-circumferential upper source electrodes except for a pad region. The second protective film covers the first protective film and at least a part of the one or more second conductivity type rings.

公开(公告)号：US20170125575A1

公开(公告)日：2017-05-04

申请号：US15403381

申请日：2017-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  MASAO UCHIDA ,  NOBUYUKI HORIKAWA ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L27/06

CPC classification number: H01L29/7803 ,  H01L21/28 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/80

Abstract: In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.