公开(公告)号：US20200303506A1

公开(公告)日：2020-09-24

申请号：US16776477

申请日：2020-01-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA ,  ATSUSHI OHOKA

IPC: H01L29/36 ,  H01L21/02 ,  H01L29/16 ,  H01L27/088 ,  H01L29/78

Abstract: Variations in device characteristics in a plane parallel to the principal surface of a semiconductor wafer are suppressed. A semiconductor epitaxial wafer includes a semiconductor wafer and a first conductivity type semiconductor epitaxial layer that is disposed on a principal surface of the semiconductor wafer and contains a first conductivity type impurity, and the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer have a positive correlation in a plane parallel to the principal surface of the semiconductor wafer.

公开(公告)号：US20180061980A1

公开(公告)日：2018-03-01

申请号：US15667895

申请日：2017-08-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/08 ,  H01L29/26 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7815 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/823481 ,  H01L27/085 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/0684 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/26 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7811

Abstract: A semiconductor device including a main region, a sense region, a separation region electrically isolating the main and sense region regions includes a first semiconductor layer positioned on the main surface of a semiconductor substrate, a plurality of main cells disposed in the main region, and a plurality of sense cells disposed in the sense region. Source regions of the main cell become conductive with a source electrode and source regions of the sense cell become conductive with a sense electrode. The separation region includes a plurality of second conductivity type separation body regions and a barrier region and is disposed within a first semiconductor layer and is disposed to abut on the surface of the first semiconductor layer.

公开(公告)号：US20190245052A1

公开(公告)日：2019-08-08

申请号：US16255875

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  NOBUYUKI HORIKAWA ,  MASAO UCHIDA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L23/528

Abstract: The silicon carbide semiconductor device includes a plurality of unit cells each having an MISFET structure and provided on a silicon carbide semiconductor substrate. A gate upper electrode disposed adjacent to the plurality of unit cells includes a gate pad and gate global wires. When viewed in plan, gate electrodes do not overlap with the gate pad.

公开(公告)号：US20190244879A1

公开(公告)日：2019-08-08

申请号：US16255874

申请日：2019-01-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  NOBUYUKI HORIKAWA ,  MASAO UCHIDA

IPC: H01L23/482 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78

Abstract: A silicon carbide semiconductor device includes an upper gate electrode including a gate pad and a gate wiring line, and an upper source electrode including first and second source pads. The gate wiring line includes a gate global wiring line extending to encircle the source pads, and a gate connection wiring line. The upper source electrode includes an outer periphery source wiring line extending to encircle the gate global wiring line, and first and second source connections connecting the outer periphery source wiring line to the first and second source pads, respectively. The gate global wiring line includes a first portion, a second portion, and a third portion. The first portion is split at a first substrate corner and a second substrate corner and lies between the first substrate corner and the second substrate corner.splitsplit

公开(公告)号：US20180277636A1

公开(公告)日：2018-09-27

申请号：US15911236

申请日：2018-03-05

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUTOMU KIYOSAWA ,  ATSUSHI OHOKA

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/32 ,  H01L29/872 ,  H01L29/08 ,  H01L29/78 ,  H01L21/66 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02634 ,  H01L21/0465 ,  H01L22/12 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/41741 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/872

Abstract: Semiconductor device 101 includes semiconductor substrate 10, drift layer 20, first electrode 50, and second electrode 60. Semiconductor substrate 10 is of a first conductivity type and is formed of a silicon carbide semiconductor, a gallium nitride semiconductor, or the like. For example, semiconductor substrate 10 is an n-type silicon carbide semiconductor substrate. Drift layer 20 is an epitaxial semiconductor layer of the first conductivity type which is formed on upper surface 10a of semiconductor substrate 10 by epitaxial growth. Drift layer 20 is formed of for example, an n-type silicon carbide semiconductor. Drift layer 20 has a thickness of t. For example, the thickness t is between about 5 μm and about 100 μm (inclusive).

公开(公告)号：US20180151719A1

公开(公告)日：2018-05-31

申请号：US15812430

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUNEICHIRO SANO ,  ATSUSHI OHOKA ,  TSUTOMU KIYOSAWA ,  OSAMU ISHIYAMA ,  TAKAYUKI WAKAYAMA ,  KOUICHI SAITOU ,  TAKASHI HASEGAWA ,  DAISUKE SHINDO ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L23/31 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L23/3192 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42356

Abstract: A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film. The first protective film covers the inner-circumferential upper source electrode, the upper gate electrode, and an inner side surface of the one or more outer-circumferential upper source electrodes except for a pad region. The second protective film covers the first protective film and at least a part of the one or more second conductivity type rings.

公开(公告)号：US20170125575A1

公开(公告)日：2017-05-04

申请号：US15403381

申请日：2017-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI OHOKA ,  MASAO UCHIDA ,  NOBUYUKI HORIKAWA ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L27/06

CPC classification number: H01L29/7803 ,  H01L21/28 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/80

Abstract: In the silicon carbide semiconductor element, a second silicon carbide semiconductor layer that is in contact with the surface of a first silicon carbide semiconductor layer has at least an upper layer including a dopant of a first conductivity type at a high concentration. Above a junction field effect transistor (JFET) region interposed between body regions that are disposed in the first silicon carbide semiconductor layer so as to be spaced from each other, the silicon carbide semiconductor element has a channel removed region, which is a cutout formed by removing a high concentration layer from the front surface side of the second silicon carbide semiconductor layer, the high concentration layer having a higher dopant concentration than at least the dopant concentration of the JFET region. The width of the channel removed region is smaller than that of the JFET region.