公开(公告)号：US20200266268A1

公开(公告)日：2020-08-20

申请号：US16726982

申请日：2019-12-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKASHI HASEGAWA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/47

Abstract: A semiconductor device includes a silicon carbide semiconductor layer, a termination region disposed in the silicon carbide semiconductor layer, an insulating film covering part of the termination region, an electrode disposed on the silicon carbide semiconductor layer, a seal ring disposed on remaining part of the termination region and surrounding the electrode, and a passivation film covering the insulating film and the seal ring. Assuming that an outer peripheral end of the seal ring and an outer peripheral end of the passivation film have distance L2 at a side of the silicon carbide semiconductor layer, the outer peripheral end of the seal ring and the outer peripheral end of the passivation film have distance L1 at a corner, and the outer peripheral end of the passivation film at the corner has radius of curvature R1, L1>L2 and R1≥L2 are satisfied.

公开(公告)号：US20190165119A1

公开(公告)日：2019-05-30

申请号：US16188332

申请日：2018-11-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TAKASHI HASEGAWA ,  KOUICHI SAITOU ,  CHIAKI KUDOU

IPC: H01L29/45 ,  H01L23/535 ,  H01L29/40 ,  H01L21/311 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L29/456 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/324 ,  H01L21/76877 ,  H01L23/535 ,  H01L29/401

Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.

公开(公告)号：US20190103463A1

公开(公告)日：2019-04-04

申请号：US16140776

申请日：2018-09-25

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： KOUICHI SAITOU

IPC: H01L29/16 ,  H01L23/544 ,  H01L21/033 ,  H01L21/308 ,  H01L29/78 ,  H01L21/04

Abstract: A semiconductor device includes a bulk substrate, and an epitaxial layer formed on a surface of the bulk substrate. A part of the surface of the bulk substrate is an alignment region including an alignment pattern defined by at least one recess or one protrusion. An ion-injected layer is formed in at least a part of the alignment region.

公开(公告)号：US20190080976A1

公开(公告)日：2019-03-14

申请号：US16112116

申请日：2018-08-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： CHIAKI KUDOU ,  TAKASHI HASEGAWA ,  KOUICHI SAITOU

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L29/16 ,  H01L29/78 ,  H01L29/872 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.

公开(公告)号：US20180151719A1

公开(公告)日：2018-05-31

申请号：US15812430

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： TSUNEICHIRO SANO ,  ATSUSHI OHOKA ,  TSUTOMU KIYOSAWA ,  OSAMU ISHIYAMA ,  TAKAYUKI WAKAYAMA ,  KOUICHI SAITOU ,  TAKASHI HASEGAWA ,  DAISUKE SHINDO ,  OSAMU KUSUMOTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L23/31 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L23/3192 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42356

Abstract: A silicon carbide semiconductor device includes a first conductivity type silicon carbide substrate having an active region and a termination region surrounding the active region, a plurality of unit cells located in the active region, and a termination structure located in the termination region. Each unit cell is provided with a transistor structure. The termination structure includes the silicon carbide semiconductor layer, a second conductivity type second body region surrounding the active region, one or more second conductivity type rings surrounding the second body region, one or more outer-circumferential upper source electrodes surrounding the active region, and an upper gate electrode. The silicon carbide semiconductor device further includes a first protective film and a second protective film. The first protective film covers the inner-circumferential upper source electrode, the upper gate electrode, and an inner side surface of the one or more outer-circumferential upper source electrodes except for a pad region. The second protective film covers the first protective film and at least a part of the one or more second conductivity type rings.

公开(公告)号：US20160315203A1

公开(公告)日：2016-10-27

申请号：US15089542

申请日：2016-04-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKAYUKI WAKAYAMA

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6606

Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to direction of crystal orientations of the semiconductor substrate.

Abstract translation: 根据本公开的一个方面的半导体器件包括具有第一导电类型并具有主表面和背表面的半导体衬底，具有第一导电类型并设置在主表面上的碳化硅半导体层，具有 第二导电类型并且设置在碳化硅半导体层内，具有第二导电类型并且设置在碳化硅半导体层内的边缘终端区域，包围阻挡区域的边缘终端区域，设置在碳化硅半导体层上的第一电极 以及设置在所述背面上的第二电极，其中，所述阻挡区域中的每一个与所述碳化硅半导体层具有多边形边界，并且所述多边形边界的每一侧相对于所述多边形边界的角度为0°至5° -20>半导体衬底的晶体取向方向。

公开(公告)号：US20160308072A1

公开(公告)日：2016-10-20

申请号：US15089383

申请日：2016-04-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKAYUKI WAKAYAMA ,  MASASHI HAYASHI ,  TATSUYA KUNISATO

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6606

Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, a guard ring region having a second conductivity type and disposed within the silicon carbide semiconductor layer, a floating region having the second conductivity type and disposed within the silicon carbide semiconductor layer, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate, wherein the guard ring region and the floating region each include a pair of a high-concentration region having the second conductivity type and a low-concentration region having the second conductivity type.

Abstract translation: 根据本公开的一个方面的半导体器件包括具有第一导电类型并具有主表面和背表面的半导体衬底，具有第一导电类型的碳化硅半导体层并且设置在半导体衬底的主表面上 具有第二导电类型并且设置在碳化硅半导体层内的保护环区域，具有第二导电类型的浮动区域并且设置在碳化硅半导体层内，设置在碳化硅半导体层上的第一电极和第二电极 设置在半导体衬底的背面上的电极，其中保护环区域和浮置区域各自包括一对具有第二导电类型的高浓度区域和具有第二导电类型的低浓度区域。