公开(公告)号：US20160308072A1

公开(公告)日：2016-10-20

申请号：US15089383

申请日：2016-04-01

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  KOUICHI SAITOU ,  TAKAYUKI WAKAYAMA ,  MASASHI HAYASHI ,  TATSUYA KUNISATO

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/402 ,  H01L29/6606

Abstract: A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface of the semiconductor substrate, a guard ring region having a second conductivity type and disposed within the silicon carbide semiconductor layer, a floating region having the second conductivity type and disposed within the silicon carbide semiconductor layer, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface of the semiconductor substrate, wherein the guard ring region and the floating region each include a pair of a high-concentration region having the second conductivity type and a low-concentration region having the second conductivity type.

Abstract translation: 根据本公开的一个方面的半导体器件包括具有第一导电类型并具有主表面和背表面的半导体衬底，具有第一导电类型的碳化硅半导体层并且设置在半导体衬底的主表面上 具有第二导电类型并且设置在碳化硅半导体层内的保护环区域，具有第二导电类型的浮动区域并且设置在碳化硅半导体层内，设置在碳化硅半导体层上的第一电极和第二电极 设置在半导体衬底的背面上的电极，其中保护环区域和浮置区域各自包括一对具有第二导电类型的高浓度区域和具有第二导电类型的低浓度区域。

公开(公告)号：US20170077087A1

公开(公告)日：2017-03-16

申请号：US15342023

申请日：2016-11-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： NOBUYUKI HORIKAWA ,  OSAMU KUSUMOTO ,  MASASHI HAYASHI ,  MASAO UCHIDA

IPC: H01L27/06 ,  H01L29/41 ,  H01L29/868 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0605 ,  H01L27/04 ,  H01L27/0727 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/41 ,  H01L29/78 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868

Abstract: A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate line region are each disposed to be sandwiched between the diode region and the diode region, and a gate electrode on the gate pad region and the gate line region is formed on an insulating film formed on an epitaxial layer. Thus, breakdown of the insulating film in the gate region can be prevented without causing deterioration in quality of the gate insulating film, upon switching and avalanche breakdown.

Abstract translation: 碳化硅半导体器件包括晶体管区域，二极管区域，栅极线区域和栅极焊盘区域。 栅极区域和栅极线区域分别被设置为夹在二极管区域和二极管区域之间，并且栅极区域上的栅极电极和栅极线区域形成在形成在外延层上的绝缘膜上。 因此，能够防止栅极绝缘膜在开关和雪崩击穿时的栅极区域的绝缘膜的破坏，而不会导致栅极绝缘膜的质量劣化。

公开(公告)号：US20150255544A1

公开(公告)日：2015-09-10

申请号：US14632895

申请日：2015-02-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： MASAO UCHIDA ,  MASASHI HAYASHI ,  KOUTAROU TANAKA

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L21/04 ,  H01L29/872 ,  H01L29/47 ,  H01L29/45 ,  H01L21/02 ,  H01L29/812 ,  H01L29/36

CPC classification number: H01L29/1608 ,  H01L21/0485 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7828 ,  H01L29/872

Abstract: A semiconductor device includes first and second second-conductivity-type region groups containing multiple second-conductivity-type regions that are disposed on a first silicon carbide semiconductor layer of a first conductivity type, arrayed in parallel following one direction with a space between each other, and first and second electrodes disposed on the first silicon carbide semiconductor layer and forming a Schottky junction with the first silicon carbide semiconductor layer. The first electrode covers a position where a distance from adjacent first and second second-conductivity-type regions included in a first second-conductivity-type region group, and a distance from a third second-conductivity-type region included in a second second-conductivity-type region group and adjacent to the first and second second-conductivity-type regions, are equal. A Schottky barrier between the first electrode and the first silicon carbide semiconductor layer is larger than a Schottky barrier between the second electrode and the first silicon carbide semiconductor layer.

Abstract translation: 半导体器件包括第一和第二第二导电型区域组，其包含多个第二导电类型区域，所述第二导电类型区域设置在第一导电类型的第一碳化硅半导体层上，并排沿着一个方向并排放置 以及设置在第一碳化硅半导体层上并与第一碳化硅半导体层形成肖特基结的第一和第二电极。 第一电极覆盖从包括在第一第二导电类型区域组中的相邻第一和第二第二导电类型区域到与包括在第二第二导电类型区域组中的第三第二导电类型区域的距离的位置， 导电类型区域组并且与第一和第二第二导电类型区域相邻。 第一电极和第一碳化硅半导体层之间的肖特基势垒大于第二电极和第一碳化硅半导体层之间的肖特基势垒。