公开(公告)号：US20230387135A1

公开(公告)日：2023-11-30

申请号：US18231830

申请日：2023-08-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/10 ,  H01L29/24

CPC classification number: H01L27/1225 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1266 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/1033 ,  H01L29/24

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

公开(公告)号：US11812599B2

公开(公告)日：2023-11-07

申请号：US17670248

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Noriyuki Sato ,  Sarah Atanasov ,  Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Hui Jae Yoo ,  Van H. Le

IPC: G11C8/00 ,  H10B12/00 ,  H01L27/12 ,  G11C11/4096

CPC classification number: H10B12/00 ,  G11C11/4096 ,  H01L27/124 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1266

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：US11791350B2

公开(公告)日：2023-10-17

申请号：US17701961

申请日：2022-03-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yasuharu Hosaka ,  Satoru Idojiri ,  Kenichi Okazaki ,  Hiroki Adachi ,  Daisuke Kubota

IPC: H01L51/52 ,  H01L27/12 ,  H01L21/683 ,  H01L29/66 ,  H01L29/786 ,  H10K59/121

CPC classification number: H01L27/1266 ,  H01L21/6835 ,  H01L27/1218 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78603 ,  H01L29/78648 ,  H01L2221/6835 ,  H01L2221/68386 ,  H10K59/1213

Abstract: A peeling method at low cost with high mass productivity is provided. A resin layer having a thickness greater than or equal to 0.1 μm and less than or equal to 3 μm is formed over a formation substrate using a photosensitive and thermosetting material, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, the resin layer is irradiated with light using a linear laser device, and the transistor and the formation substrate are separated from each other. A first region and a second region which is thinner than the first region or an opening can be formed in the resin layer. In the case of forming a conductive layer functioning as an external connection terminal or the like to overlap with the second region or the opening of the resin layer, the conductive layer is exposed.

公开(公告)号：US11791344B2

公开(公告)日：2023-10-17

申请号：US17377787

申请日：2021-07-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei Toyotaka ,  Kei Takahashi ,  Hideaki Shishido ,  Koji Kusunoki

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/49 ,  H01L29/786 ,  H10K59/126 ,  H10K59/121

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1266 ,  H01L29/045 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78648 ,  H10K59/126 ,  H10K59/1213

Abstract: A novel display device or the like in which a transistor connected to a scan line has small gate capacitance is provided. A novel display device or the like in which a scan line has low resistance is provided. A novel display device or the like in which pixels can be arranged with high density is provided. A novel display device or the like that can be manufactured without an increase in cost is provided. In a transistor including a first gate electrode and a second gate electrode, the first gate electrode is formed using a metal material with low resistance and the second gate electrode is formed using a metal oxide material that can reduce oxygen vacancies in an oxide semiconductor layer. The first gate electrode is connected to the scan line, and the second gate electrode is connected to a wiring to which a constant potential is supplied.

公开(公告)号：US11735462B2

公开(公告)日：2023-08-22

申请号：US18088602

申请日：2022-12-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/792 ,  G11C8/16 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B20/20

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1579 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/30105 ,  H10B12/05 ,  H10B20/20

Abstract: A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

公开(公告)号：US20230163135A1

公开(公告)日：2023-05-25

申请号：US17614662

申请日：2021-02-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaoyan Zhu ,  Chuanxiang Xu ,  Ling Li ,  Hua Huang

IPC: H01L27/12 ,  H01L21/683

CPC classification number: H01L27/1218 ,  H01L27/1266 ,  H01L21/6835 ,  H01L2221/6835

Abstract: A display substrate includes a first display region and a second display region. The display substrate may include: a first base substrate; a second base substrate; a first barrier layer and a light emitting unit. The first base substrate includes a first through region penetrating the first base substrate, and the first barrier layer includes a second through region penetrating the first barrier layer. The second base substrate includes a first substrate sub-portion located in the first display region, the first substrate sub-portion penetrates the second through region, and at least a portion of the first substrate sub-portion is located in the first through region. The display substrate includes a recessed portion. The second base substrate includes a first surface located in the first display region and a second surface located in the second display region, and the first surface and the second surface are formed as a flat surface.

公开(公告)号：US20190198803A1

公开(公告)日：2019-06-27

申请号：US16251144

申请日：2019-01-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toru TAKAYAMA ,  Junya MARUYAMA ,  Yumiko OHNO

IPC: H01L51/52 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  H01L51/56 ,  H01L51/00

CPC classification number: H01L51/5246 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1266 ,  H01L27/3244 ,  H01L27/3276 ,  H01L29/78672 ,  H01L51/0097 ,  H01L51/5237 ,  H01L51/5243 ,  H01L51/5253 ,  H01L51/56 ,  H01L2221/68368 ,  H01L2227/326 ,  H01L2251/5323

Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.

公开(公告)号：US20180342536A1

公开(公告)日：2018-11-29

申请号：US15978464

申请日：2018-05-14

Applicant: Japan Display Inc.

Inventor： Isao Suzumura ,  Hajime Watakabe ,  Akihiro Hanada ,  Hirokazu Watanabe ,  Yohei Yamaguchi ,  Marina Shiokawa ,  Ryotaro Kimura

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1333

CPC classification number: H01L27/124 ,  G02F1/133305 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  G02F2202/104 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1266 ,  H01L27/127 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/78648 ,  H01L29/78678 ,  H01L29/7869

Abstract: The purpose of the invention is to form a flexible display device where the substrate is made of resin, wherein the TFT can be annealed in high temperature; consequently, a reliability of the TFT is improved. The concrete measure is as follows. A display device having a pixel electrode and a TFT including a semiconductor layer on a substrate comprising: a source region of the semiconductor layer connects with a source electrode, a drain region of the semiconductor layer connects with a drain electrode; the pixel electrode connects with the source electrode; the drain electrode connects with a video signal line; a distance between the drain electrode and the substrate is smaller than a distance between the semiconductor and the substrate, the semiconductor layer is formed between the pixel electrode and the substrate.

公开(公告)号：US20180277572A1

公开(公告)日：2018-09-27

申请号：US15540549

申请日：2017-06-13

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Yun YU

IPC: H01L27/12 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L27/1218 ,  H01L24/05 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/1266 ,  H01L2224/04026 ,  H01L2224/27003 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/8385

Abstract: The present disclosure relates to a flexible display panel and the manufacturing method thereof. The flexible display panel includes a display area, a non-display area in a rim of the display area, and a chip bonding area arranged on the non-display area. The chip bonding area includes a supporting substrate, an adhesive layer, a flexible substrate, an inorganic insulation layer, an anisotropic conductive film (ACF) and a chip. The supporting substrate includes a main board and a protrusion for enhancing the bonding reliability. With such structure of the supporting substrate, the supporting substrate may greatly enhance the reliability of the bonding process with respect to the chip.

公开(公告)号：US10020377B2

公开(公告)日：2018-07-10

申请号：US15345360

申请日：2016-11-07

Applicant: Pragmatic Printing Ltd

Inventor： John James Gregory ,  Richard David Price

IPC: G03F7/20 ,  H01L27/22 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/66477 ,  G03F7/2022 ,  H01L27/1266 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78696

Abstract: A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor channel connecting the first and second terminals and a gate terminal to which a potential may be applied to control a conductivity of the channel. The method comprises a first exposure of a photoresist from above the substrate using a mask and a second exposure from below, wherein in the second exposure the first and second terminals shield a part of the photoresist from exposure. An intermediate step reduces the solubility of the photoresist exposed in the first exposure. A window is formed in the photoresist at the location which was shielded by the mask, but exposed to radiation from below. Semiconductor material, dielectric material and conductor material are deposited inside the window to form a semiconductor channel, gate dielectric, and a gate terminal, respectively.