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    SRAM CELLS
    11.
    发明申请
    SRAM CELLS 有权

    公开(公告)号：US20150371708A1

    公开(公告)日：2015-12-24

    申请号：US14767442

    申请日：2014-02-06

    Applicant: SURECORE LIMITED

    Inventor： Andrew PICKERING

    IPC: G11C14/00 ,  G11C11/404 ,  G11C11/419

    CPC classification number: G11C14/0063 ,  G11C8/14 ,  G11C11/404 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

    Abstract: There is provided a memory unit that comprises a plurality of memory cell groups, each memory cell group comprising a plurality of memory cells that are each operatively connected to a first local bit line and a second local bit line by respective first and second access transistors, and each memory cell being associated with a word line configured to control the first and second access transistors of the memory cell. The first and second local bit lines of each memory cell group being operatively connected to respective first and second column bit lines by respective first and second group access switches, the first group access switch being configured to be controlled by the second column bit line, and the second group access switch being configured to be controlled by the first column bit line.

    Abstract translation: 提供了包括多个存储单元组的存储器单元，每个存储单元组包括多个存储单元，每个存储单元通过相应的第一和第二存取晶体管可操作地连接到第一局部位线和第二局部位线， 并且每个存储器单元与被配置为控制存储器单元的第一和第二存取晶体管的字线相关联。 每个存储单元组的第一和第二局部位线通过相应的第一和第二组访问开关可操作地连接到相应的第一和第二列位线，第一组访问开关被配置为由第二列位线控制，以及 第二组访问开关被配置为由第一列位线控制。

    NON-VOLATILE REGISTER AND NON-VOLATILE SHIFT REGISTER
    12.
    发明申请
    NON-VOLATILE REGISTER AND NON-VOLATILE SHIFT REGISTER 审中-公开
    非易失性寄存器和非易失性移位寄存器

    公开(公告)号：US20150325302A1

    公开(公告)日：2015-11-12

    申请号：US14805211

    申请日：2015-07-21

    Applicant: FlashSilicon Incorporation

    Inventor： Lee WANG

    IPC: G11C16/14

    CPC classification number: G11C16/14 ,  G11C14/00 ,  G11C14/0054 ,  G11C14/0063 ,  G11C19/28

    Abstract: Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.

    Abstract translation: 公开了非易失性寄存器（NVR）和非易失性移位寄存器（NVSR）器件。 本发明的创新的NVR和NVSR设备可以将非易失性存储器元件中存储的非易失性数据快速加载到其对应的静态存储器元件中，以在数字电路中快速和恒定地引用。 根据本发明，从非易失性存储器到静态存储器的加载过程是直接的过程，而不需要经历访问非易失性存储器的常规过程，从非易失性存储器的感测和加载到数字寄存器中并且移位 注册

    10T NVSRAM cell and cell operations
    13.
    发明授权
    10T NVSRAM cell and cell operations 有权
    10T NVSRAM单元和单元操作

    公开(公告)号：US09177645B2

    公开(公告)日：2015-11-03

    申请号：US14058227

    申请日：2013-10-19

    Applicant: Aplus Flash Technology, Inc

    Inventor： Hsing-Ya Tsao ,  Peter Wung Lee

    IPC: G11C14/00

    CPC classification number: G11C14/0063

    Abstract: A 10T NVSRAM cell is provided with a bottom HV NMOS Select transistor in each 3T FString removed from traditional 12T NVSRAM cell. A Recall operation by reading a stored ΔVt state of flash transistors into each SRAM cell uses a charge-sensing scheme rather than the current-sensing scheme, with all other key operations unchanged. The Recall operation works under any ramping rate of SRAM's power line voltage and Flash gate signal which can be set higher than only Vt0 or both Vt0 and Vt1. Alternatively, the Store operation can use a current charging scheme from a Fpower line to the paired Q and QB nodes of each SRAM cell through a paired Flash Voltage Follower that stored ΔVtp≧1.0V. The Recall operation in this alternative embodiment is to use a 7-step approach with the FN-channel erase, FN-channel program and FN-edge program schemes, including 2-step SRAM amplification.

    Abstract translation: 10T NVSRAM单元提供有从传统12T NVSRAM单元移除的每个3T FString中的底部HV NMOS选择晶体管。 通过将闪存晶体管的存储的＆Dgr; Vt状态读入每个SRAM单元的回收操作使用电荷感测方案而不是电流感测方案，其他所有关键操作都不变。 调用操作在SRAM的电源线电压和闪存栅极信号的任何斜坡率下工作，其可以被设置为高于仅Vt0或者Vt0和Vt1两者。 或者，存储操作可以使用存储＆Dgr;Vtp≥1.0V的成对闪存电压跟随器从Fpower线路到每个SRAM单元的成对Q和QB节点的当前充电方案。 该替代实施例中的调用操作是使用包括2步SRAM放大的FN通道擦除，FN通道程序和FN边缘程序方案的7步法。

    Non-Volatile Semiconductor Storage Device
    16.
    发明申请
    Non-Volatile Semiconductor Storage Device 有权
    非易失性半导体存储设备

    公开(公告)号：US20150311219A1

    公开(公告)日：2015-10-29

    申请号：US14647009

    申请日：2013-10-31

    Applicant: FLOADIA CORPORATION

    Inventor： Yasuhiro Taniguchi ,  Kosuke Okuyama

    IPC: H01L27/115 ,  H01L27/11 ,  H01L29/788 ,  G11C14/00 ,  H01L29/36

    CPC classification number: H01L27/11521 ,  G11C14/0063 ,  G11C16/0441 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1156 ,  H01L29/36 ,  H01L29/788 ,  H01L29/7881

    Abstract: To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate structure. In a non-volatile semiconductor memory device (1), while each of the memory transistor (MGA1) and the switch transistor (SGA) is made to have a single-layer gate structure, when a selected memory cell (3a) is turned on by applying a high voltage to one end of a memory transistor (MGA1) from a source line (SL) during data programming and applying a low voltage to one end of the switch transistor (SGA) from a bit line (BL1), a voltage drop occurs in a low-concentration impurity extension region (ET2) in the memory transistor (MGA1) between the source line (SL) and the bit line (BL1) to generate an intense electric field, and charge can be injected into the floating gate (FG) by source side injection using the intense electric field.

    Abstract translation: 提出即使在单层栅极结构中也能够通过源极侧注入将电荷注入浮置栅极的非易失性半导体存储器件。 在非易失性半导体存储器件（1）中，当存储晶体管（MGA1）和开关晶体管（SGA）中的每一个被制成具有单层栅极结构时，当选择的存储单元（3a）导通时 通过在数据编程期间从源极线（SL）向存储晶体管（MGA1）的一端施加高电压，并从位线（BL1）向开关晶体管（SGA）的一端施加低电压， 在源极线（SL）和位线（BL1）之间的存储晶体管（MGA1）中的低浓度杂质扩展区域（ET2）中产生下降，产生强电场，电荷可以注入浮置栅极 （FG）通过使用强电场的源侧注入。

    Method of accessing a memory device
    17.
    发明授权
    Method of accessing a memory device 有权
    访问存储设备的方法

    公开(公告)号：US09076524B2

    公开(公告)日：2015-07-07

    申请号：US14283117

    申请日：2014-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Federico Pio

    IPC: G11C16/06 ,  G11C14/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/12 ,  G06F21/60 ,  G11C5/14 ,  G11C16/30 ,  G11C7/22 ,  G11C7/10 ,  G11C11/56

    CPC classification number: G11C5/147 ,  G06F12/0246 ,  G06F21/60 ,  G06F2212/7204 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/5621 ,  G11C11/5671 ,  G11C14/0063 ,  G11C14/009 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/107 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

    Abstract: A method is provided for accessing a memory device. The method includes programming data in a plurality of cells of the memory device in a first programming operation. The first programming operation uses a first memory instruction including at least one first parameter representative of at least one first threshold voltage value for said programming. The method further includes re-programming at least a portion of the data in the plurality of cells in a second programming operation. The second programming operation uses a second memory instruction including at least one second parameter representative of at least one second threshold voltage value for said re-programming, wherein said re-programming provides bit manipulation of the portion of the data.

    Abstract translation: 提供了一种访问存储器件的方法。 该方法包括在第一编程操作中在存储器件的多个单元中编程数据。 第一编程操作使用包括代表用于所述编程的至少一个第一阈值电压值的至少一个第一参数的第一存储器指令。 该方法还包括在第二编程操作中对多个单元中的数据的至少一部分进行重新编程。 第二编程操作使用包括表示用于所述重新编程的至少一个第二阈值电压值的至少一个第二参数的第二存储器指令，其中所述重新编程提供对所述数据的该部分的位操作。

    MEMORY CELL
    18.
    发明申请
    MEMORY CELL 有权
    记忆体

    公开(公告)号：US20150162063A1

    公开(公告)日：2015-06-11

    申请号：US14564212

    申请日：2014-12-09

    Applicant: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

    Inventor： Johannes MUELLER

    IPC: G11C11/22 ,  G11C14/00

    CPC classification number: G11C11/221 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/5657 ,  G11C14/0027 ,  G11C14/0063

    Abstract: Nonvolatile storage with long memory endurance having the advantages of easy manufacturability is obtained by using a memory cell having an information storage element including a ferroelectric material, and operating the memory cell in a volatile operating mode and a nonvolatile operating mode. The option of operating the memory cell in the volatile operating mode enables the associated advantages of high memory speed at long endurance, wherein, however, the option of operating the memory cell in the nonvolatile operating mode can bridge gaps in the power supply.

    Abstract translation: 通过使用具有包含铁电材料的信息存储元件的存储单元，并且以易失性操作模式和非易失性操作模式操作存储单元，获得具有易于制造性优点的具有长存储耐久性的非易失存储器。 在易失性操作模式下操作存储单元的选项使得能够在长时间耐用性下具有高存储器速度的相关优点，然而，在非易失性操作模式下操作存储单元的选项可以弥补电源中的间隙。

    Pseudo-8T NVSRAM cell with a charge-follower
    19.
    发明授权
    Pseudo-8T NVSRAM cell with a charge-follower 有权
    带有充电跟随器的伪8T NVSRAM单元

    公开(公告)号：US08971113B2

    公开(公告)日：2015-03-03

    申请号：US14064220

    申请日：2013-10-28

    Applicant: Aplus Flash Technology, Inc

    Inventor： Peter Wung Lee

    IPC: G11C11/34 ,  G11C14/00

    CPC classification number: G11C14/0063

    Abstract: The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ΔVQ-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM's VDD line and ramping down SRAM's VSS line.

    Abstract translation: 本发明公开了一种具有6T SRAM单元的10T NVSRAM单元，具有4T闪存单元和一个专用的基于闪存的充电器。 此外，还公开了在单元格布局的顶部和底部的两个相邻的8T NVSRAM单元之间具有共享的基于闪存的充电器的伪8T NVSRAM单元，以进一步将单元大小减小20％。 与12T NVSRAM单元的现有技术相反，上述两个优选实施例的存储操作使用具有闪存单元的DRAM状电荷感测方案，其被配置为由基于闪存的充电器确保的电压跟随器以获得最终的＆Dgr; 每个SRAM单元的Q和QB节点的VQ-QB> 0.2V，以覆盖闪存单元器件中的所有寄生电容失配，并通过升高SRAM的VDD线并降低SRAM的VSS线来布置可靠的放大。

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