公开(公告)号：US20240379680A1

公开(公告)日：2024-11-14

申请号：US18779905

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

公开(公告)号：US20240371963A1

公开(公告)日：2024-11-07

申请号：US18770185

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

公开(公告)号：US20240365559A1

公开(公告)日：2024-10-31

申请号：US18766899

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H10B51/30 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

CPC classification number: H10B51/30 ,  H01L21/02565 ,  H01L21/02603 ,  H01L21/76816 ,  H01L21/76877 ,  H01L29/0673 ,  H01L29/24 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H10B43/20 ,  H10B43/30 ,  H10B51/20 ,  H10B99/00

Abstract: 3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

公开(公告)号：US20240365557A1

公开(公告)日：2024-10-31

申请号：US18770406

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/78 ,  H01L29/786 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/78391 ,  H01L29/785 ,  H01L29/78696 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

公开(公告)号：US20240363627A1

公开(公告)日：2024-10-31

申请号：US18767022

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Chang Chiu ,  Chia-Ching Lee ,  Chien-Hao Chen ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chi On Chui ,  Hsuan-Yu Tung ,  Chung-Chiang Wu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/6681 ,  H01L29/785

Abstract: A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.

公开(公告)号：US20240363432A1

公开(公告)日：2024-10-31

申请号：US18767282

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76229 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US20240363351A1

公开(公告)日：2024-10-31

申请号：US18765720

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/28088 ,  H01L21/0259 ,  H01L21/28185 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/0673

Abstract: In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

公开(公告)号：US20240355880A1

公开(公告)日：2024-10-24

申请号：US18757772

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/0673 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/0262 ,  H01L29/0638 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4925 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

公开(公告)号：US12107150B2

公开(公告)日：2024-10-01

申请号：US18324442

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Chi On Chui

IPC: H01L29/66 ,  C23C18/16 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/66545 ,  C23C18/1657 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66742

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.

公开(公告)号：US12101939B2

公开(公告)日：2024-09-24

申请号：US17883834

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Lu ,  Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui ,  Han-Jong Chia ,  Chenchen Jacob Wang

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B51/30

Abstract: A method of forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, the first layer stack and the second layer stack having a same layered structure that includes a dielectric material, a channel material over the dielectric material, and a source/drain material over the channel material; forming openings that extend through the first layer stack and the second layer stack; forming inner spacers by replacing portions of the source/drain material exposed by the openings with a first dielectric material; lining sidewalls of the openings with a ferroelectric material; forming gate electrodes by filling the openings with an electrically conductive material; forming a recess through the first layer stack and the second layer stack, the recess extending from a sidewall of the second layer stack toward the gate electrodes; and filling the recess with a second dielectric material.