公开(公告)号：US20160240665A1

公开(公告)日：2016-08-18

申请号：US14623843

申请日：2015-02-17

Applicant: SANDISK 3D LLC

Inventor： Yung-Tin CHEN ,  Guangle Zhou ,  Christopher Petti

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/11582 ,  H01L27/1203 ,  H01L27/2454 ,  H01L27/249 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/78642 ,  H01L45/16

Abstract: A first patterned stack and a second patterned stack are formed over a substrate, each of which includes a bottom semiconductor layer, a bottom dielectric spacer layer, a conductive material layer, and a top dielectric spacer layer. Gate dielectrics and vertical semiconductor portions are sequentially formed on each patterned stack. Vertical semiconductor portions are removed from around the second patterned stack, while masked around the first patterned stack. Electrical dopants are introduced to top regions and bottom regions of the remaining vertical semiconductor portions to form a vertical switching device that includes the first patterned stack, while the second patterned stack functions as a horizontal interconnect structure. The vertical switching device can be a transistor or a gated diode.

Abstract translation: 第一图案化堆叠和第二图案化堆叠形成在衬底上，每个衬底包括底部半导体层，底部电介质间隔层，导电材料层和顶部电介质间隔层。 栅极电介质和垂直半导体部分依次形成在每个图案化的叠层上。 垂直半导体部分从第二图案化堆叠周围移除，同时围绕第一图案化堆叠进行掩蔽。 将电掺杂物引入剩余垂直半导体部分的顶部区域和底部区域，以形成包括第一图案化叠层的垂直开关装置，而第二图案化叠层用作水平互连结构。 垂直开关器件可以是晶体管或栅极二极管。

公开(公告)号：US09373396B2

公开(公告)日：2016-06-21

申请号：US14716382

申请日：2015-05-19

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: H01L29/02 ,  G11C13/00 ,  G06F11/10 ,  H01L27/24 ,  H01L29/786 ,  H01L45/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C7/12 ,  G11C7/18 ,  G11C29/02 ,  G11C29/12

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20160133836A1

公开(公告)日：2016-05-12

申请号：US14538763

申请日：2014-11-11

Applicant: SANDISK 3D LLC

Inventor： Zhida Lan ,  Abhijit Bandyopadhyay ,  Christopher Petti ,  Li Xiao ,  Girish Nagavarapu

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/146 ,  H01L45/1683

Abstract: The manufacturing of the non-volatile storage system includes depositing one or more layers of reversible resistance-switching material for a non-volatile storage element. Prior to operation, either during manufacturing or afterwards, a forming operation is performed. In one embodiment, the forming operation includes applying a forming voltage to the one or more layers of reversible resistance-switching material to form a first region that includes a resistor and a second region that can reversibly change resistance at a low current, the resistor is formed in response to the forming condition and is not deposited on the device. In some embodiments, programming the non-volatile storage element includes applying a programming voltage that increases in voltage over time at low current but does not exceed the final forming voltage.

Abstract translation: 非易失性存储系统的制造包括为非易失性存储元件沉积一层或多层可逆电阻切换材料。 在操作之前，在制造期间或之后，进行成形操作。 在一个实施例中，形成操作包括向一个或多个可逆电阻切换材料层施加成形电压以形成包括电阻器的第一区域和可在低电流下可逆地改变电阻的第二区域，电阻器 响应于成形条件而形成，并且不会沉积在该装置上。 在一些实施例中，对非易失性存储元件的编程包括施加在低电流下随时间增加的电压但不超过最终形成电压的编程电压。

公开(公告)号：US20160020255A1

公开(公告)日：2016-01-21

申请号：US14715566

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: H01L27/24 ,  H01L45/00 ,  H01L29/786 ,  G11C13/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

公开(公告)号：US20160019961A1

公开(公告)日：2016-01-21

申请号：US14715583

申请日：2015-05-18

Applicant: SANDISK 3D LLC

Inventor： Perumal Ratnam ,  Christopher Petti ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G06F11/1048 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0033 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/1204 ,  G11C2213/71 ,  G11C2216/10 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L29/786 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1246 ,  H01L45/146

Abstract: Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

Abstract translation: 描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。 在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。 可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻 其不直接连接到本征多晶硅部分。 本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。