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    Field effect transistor and method of fabricating the same
    11.
    发明授权
    Field effect transistor and method of fabricating the same 有权
    场效应晶体管及其制造方法

    公开(公告)号：US09595610B2

    公开(公告)日：2017-03-14

    申请号：US14723673

    申请日：2015-05-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： TaeYong Kwon ,  Shigenobu Maeda ,  David Seo ,  Jae-Hwan Lee

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/7849 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785

    Abstract: A MOSFET may be formed with a strain-inducing mismatch of lattice constants that improves carrier mobility. In exemplary embodiments a MOSFET includes a strain-inducing lattice constant mismatch that is not undermined by a recessing step. In some embodiments a source/drain pattern is grown without a recessing step, thereby avoiding problems associated with a recessing step. Alternatively, a recessing process may be performed in a way that does not expose top surfaces of a strain-relaxed buffer layer. A MOSFET device layer, such as a strain-relaxed buffer layer or a device isolation layer, is unaffected by a recessing step and, as a result, strain may be applied to a channel region without jeopardizing subsequent formation steps.

    Abstract translation: 可以形成MOSFET，其具有改善载流子迁移率的晶格常数的应变诱导失配。 在示例性实施例中，MOSFET包括不会被凹陷步骤破坏的应变诱导晶格常数失配。 在一些实施例中，源/漏图案在没有凹陷步骤的情况下生长，从而避免与凹陷步骤相关的问题。 或者，可以以不暴露应变松弛缓冲层的顶表面的方式执行凹陷处理。 诸如应变松弛缓冲层或器件隔离层的MOSFET器件层不受凹陷步骤的影响，结果可能将应变施加到沟道区而不会影响随后的形成步骤。

    Semiconductor device and method of manufacturing the same
    12.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09502425B2

    公开(公告)日：2016-11-22

    申请号：US14532152

    申请日：2014-11-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Jihoon Yoon ,  Sungman Lim

    IPC: H01L27/112 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/02

    CPC classification number: H01L27/11206 ,  H01L23/5226 ,  H01L23/5252 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/42372 ,  H01L29/785 ,  H01L29/7851

    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.

    Abstract translation: 本发明构思提供半导体器件及其制造方法。 一个半导体器件包括衬底，设置在衬底上的器件隔离层，由器件隔离层限定并且具有高于器件隔离层的顶表面的顶表面的翅片型有源图案，设置在器件隔离层上的第一导电线 翅片型有源图案的边缘部分和与鳍式有源图案的边缘部分相邻的器件隔离层，以及设置在鳍式有源图案和第一导电线之间的绝缘薄层。 第一导线形成可以施加写入电压的反熔丝的栅电极。

    Fuse structure and semiconductor device including the same
    13.
    发明授权
    Fuse structure and semiconductor device including the same 有权
    保险丝结构和包括相同的半导体器件

    公开(公告)号：US09419004B2

    公开(公告)日：2016-08-16

    申请号：US14575647

    申请日：2014-12-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-Min Choi ,  Shigenobu Maeda

    IPC: H01L23/52 ,  H01L27/112 ,  H01L23/525 ,  H01L29/78 ,  H01L27/06

    CPC classification number: H01L27/11206 ,  H01L23/5256 ,  H01L27/0629 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device.

    Abstract translation: 熔丝结构包括：设置在场绝缘层中的第一鳍状图案，其包括突出在所述场绝缘层的上表面上方的上表面;所述场绝缘层上穿过所述第一鳍状图案的导电图案;第一半导体区域 位于导电图案的至少一侧，以及设置在第一鳍片图案的每一侧上的导电图案上的第一和第二触点。 熔丝结构可以包括在半导体器件中。

    LOW NOISE AND HIGH PERFORMANCE LSI DEVICE
    18.
    发明申请
    LOW NOISE AND HIGH PERFORMANCE LSI DEVICE 审中-公开
    低噪声和高性能LSI器件

    公开(公告)号：US20150311189A1

    公开(公告)日：2015-10-29

    申请号：US14791770

    申请日：2015-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shigenobu Maeda ,  Jeong-Hwan Yang

    IPC: H01L27/02 ,  H01L27/092 ,  H01L29/78

    CPC classification number: H01L27/0922 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1052 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848

    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate. For example, mechanical stress can be applied to devices that operate in high-speed digital settings, while devices that operate in analog or RF signal settings, in which electrical noise such as flicker noise that may be introduced by applied stress may degrade performance, have no stress applied.

    Abstract translation: 在其中使用NMOS器件和PMOS器件的半导体器件中，以不同的模式（例如模拟和数字模式）来执行应力工程，根据所需的操作模式，对特定器件有选择地施加应力工程。 也就是说，适当的机械应力，即拉伸或压缩，可以施加到和/或从设备（即，NMOS和/或PMOS器件）中去除和/或从器件去除，不仅基于它们的导电类型，即n型或p- 类型，而且还在于其预期的操作应用，例如模拟/数字，低电压/高电压，高速/低速，噪声敏感/噪声不敏感等。结果是个体的性能 设备根据其运行模式进行优化。 例如，机械应力可以应用于在高速数字设置中工作的设备，而在模拟或RF信号设置中工作的设备，其中可能由施加的应力引入的诸如闪烁噪声的电噪声可能降低性能，具有 没有施加应力。

    Semiconductor device including fuse structure
    19.
    发明授权
    Semiconductor device including fuse structure 有权
    半导体器件包括熔丝结构

    公开(公告)号：US09087842B2

    公开(公告)日：2015-07-21

    申请号：US14304750

    申请日：2014-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyun-Min Choi ,  Shigenobu Maeda ,  Ji-Hoon Yoon ,  Sung-Man Lim

    IPC: H01L27/10 ,  H01L29/00 ,  H01L23/525 ,  H01L23/522

    CPC classification number: H01L23/5256 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.

    Abstract translation: 半导体器件包括具有熔丝区域和器件区域的衬底; 保险丝区域的绝缘层中的熔丝结构，以及设备区域的绝缘层中的线结构。 熔丝结构包括熔丝通孔，熔丝线与熔丝通孔图案的顶端电连接并沿一个方向延伸。 导线结构包括导线通孔，电线连接到导线通孔的顶端并沿第一方向延伸的导线。 保险丝通孔的第一方向上的宽度小于电线通路的第一方向上的宽度。

    Semiconductor fabrication process and method of optimizing the same
    20.
    发明授权
    Semiconductor fabrication process and method of optimizing the same 有权

    公开(公告)号：US11791184B2

    公开(公告)日：2023-10-17

    申请号：US17719722

    申请日：2022-04-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiho Kim ,  Minhyeok Kwon ,  Shigenobu Maeda ,  Jooyeok Seo ,  Minuk Lee

    IPC: H01L21/67 ,  G05B19/418

    CPC classification number: H01L21/67276 ,  G05B19/41865 ,  G05B2219/32291 ,  G05B2219/33034 ,  G05B2219/45031

    Abstract: The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

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