公开(公告)号：US20200219885A1

公开(公告)日：2020-07-09

申请号：US16820006

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L21/28 ,  H01L29/49 ,  H01L29/06

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US20190067278A1

公开(公告)日：2019-02-28

申请号：US15952798

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeoungwon Seo ,  Wonsok Lee ,  Min Hee Cho ,  Hyun-Sook Byun

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation layer. A word line structure is in a trench formed in an upper portion of the substrate. The word line structure includes a gate insulation pattern covering an inner surface of the trench. A gate electrode pattern is on the gate insulation pattern. A first work function pattern is between the gate insulation pattern and the gate electrode pattern. A second work function pattern is on the first work function pattern and extends along a side surface of the gate electrode pattern. The first work function pattern has a top surface at a level below that of a bottom surface of the gate electrode pattern. The first work function pattern has a work function greater than that of the second work function pattern.

公开(公告)号：US11887653B2

公开(公告)日：2024-01-30

申请号：US17705915

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Lee ,  Min Tae Ryu ,  Wonsok Lee ,  Min Hee Cho

IPC: G11C11/418 ,  G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4085 ,  G11C11/4087 ,  H10B12/315

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

公开(公告)号：US20230354582A1

公开(公告)日：2023-11-02

申请号：US18062825

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Byeongjoo Ku ,  Keunnam Kim ,  Wonsok Lee ,  Moonyoung Jeong ,  Min Hee Cho

IPC: H01L29/94

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor device may include a bit line extending in a first direction, a semiconductor pattern on the bit line, the semiconductor pattern including first and second vertical portions, which are opposite to each other in the first direction, and a horizontal portion connecting the first and second vertical portions, first and second word lines on the horizontal portion to be adjacent to the first and second vertical portions, respectively, and a gate insulating pattern between the first vertical portion and the first word line and between the second vertical portion and the second word line. A bottom surface of the horizontal portion may be located at a height that is lower than or equal to the uppermost surface of the bit line.

公开(公告)号：US20230292490A1

公开(公告)日：2023-09-14

申请号：US18081905

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin Lee ,  Yongseok Kim ,  Mintae Ryu ,  Huije Ryu ,  Sungwon Yoo ,  Wonsok Lee ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

公开(公告)号：US20190051652A1

公开(公告)日：2019-02-14

申请号：US15952308

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Min Hee Cho ,  Bong-Soo Kim ,  Junsoo Kim ,  Satoru Yamada ,  Wonsok Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/49 ,  H01L21/28

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

公开(公告)号：US12075611B2

公开(公告)日：2024-08-27

申请号：US17481583

申请日：2021-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsok Lee ,  Min Tae Ryu ,  Woo Bin Song ,  Kiseok Lee ,  Minsu Lee ,  Min Hee Cho

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0607 ,  H10B12/05 ,  H10B12/50

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

公开(公告)号：US20240276703A1

公开(公告)日：2024-08-15

申请号：US18517126

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsok Lee ,  Juho Lee ,  Seunghyun Kim ,  Wooje Jung ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/05

Abstract: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.

公开(公告)号：US12021095B2

公开(公告)日：2024-06-25

申请号：US17376333

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon Kang ,  Buil Jung ,  Hyunmog Park ,  Wonsok Lee

IPC: H01L27/146 ,  H01L29/423

CPC classification number: H01L27/14614 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14689 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/42376

Abstract: An image sensor includes a substrate having a pixel area in which a plurality of active areas is defined. A first transistor includes a first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.

公开(公告)号：US10811408B2

公开(公告)日：2020-10-20

申请号：US15952798

申请日：2018-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeoungwon Seo ,  Wonsok Lee ,  Min Hee Cho ,  Hyun-Sook Byun

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation layer. A word line structure is in a trench formed in an upper portion of the substrate. The word line structure includes a gate insulation pattern covering an inner surface of the trench. A gate electrode pattern is on the gate insulation pattern. A first work function pattern is between the gate insulation pattern and the gate electrode pattern. A second work function pattern is on the first work function pattern and extends along a side surface of the gate electrode pattern. The first work function pattern has a top surface at a level below that of a bottom surface of the gate electrode pattern. The first work function pattern has a work function greater than that of the second work function pattern.