公开(公告)号：US10734309B2

公开(公告)日：2020-08-04

申请号：US16282682

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

IPC: H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.

公开(公告)号：US09773699B2

公开(公告)日：2017-09-26

申请号：US15000302

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Jin Lee ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Jin-Nam Kim ,  Tsukasa Matsuda ,  Wan-Soo Park ,  Nae-In Lee ,  Jae-Won Chang ,  Eun-Ji Jung ,  Jeong-Ok Cha ,  Jae-Won Hwang ,  Jung-Ha Hwang

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76882 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76864 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

公开(公告)号：US09171755B2

公开(公告)日：2015-10-27

申请号：US14453310

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Jongmin Baek ,  Dohyoung Kim ,  Tsukasa Matsuda ,  Youngwoo Cho ,  Jongseo Hong

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764 ,  H01L21/762

CPC classification number: H01L21/7682 ,  H01L21/02296 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76885

Abstract: A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

Abstract translation: 制造半导体器件的方法可以包括：在衬底上形成具有开口的层间绝缘层; 在开口和层间绝缘层上形成金属层，金属层包括在每个开口的侧壁上的侧壁部分和在每个开口的底表面上的底部，其中底部部分比 侧壁部分; 回流金属层以在开口中形成金属图案，金属图案具有位于层间绝缘层的最上表面以下的顶表面; 和/或形成覆盖开口中的金属图案的覆盖图案。

公开(公告)号：US09276116B2

公开(公告)日：2016-03-01

申请号：US14161744

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu Maeda ,  Tsukasa Matsuda ,  Hidenobu Fukutome

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/665 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.

Abstract translation: 提供半导体器件。 所述半导体器件包括：衬底上的第一鳍片;与所述第一鳍片相交的所述衬底上形成的第一栅电极，所述第一栅电极两侧的所述第一鳍片上的第一升高源极/漏极;以及第一金属合金层 在第一升高的源极/漏极的上表面和侧壁上。

公开(公告)号：US20170358519A1

公开(公告)日：2017-12-14

申请号：US15669280

申请日：2017-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Nam Kim ,  Tsukasa Matsuda ,  Rak-Hwan Kim ,  Byung-Hee Kim ,  Nae-In Lee ,  Jong-Jin Lee

IPC: H01L23/485 ,  H01L23/498 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/485 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76882 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.