公开(公告)号：US20220108921A1

公开(公告)日：2022-04-07

申请号：US17150557

申请日：2021-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyong BAE ,  Hoonseok Seo ,  Euibok Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and a 1st via structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, a 1st vertical side of the 1st via structure does not contact a barrier metal pattern while a 2nd vertical side of the 1st via structure opposite to the 1st vertical side of the 1st via structure contacts the barrier metal pattern.

公开(公告)号：US20220230956A1

公开(公告)日：2022-07-21

申请号：US17535818

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Euibok Lee ,  Wandon Kim ,  Minjoo Lee ,  Hyunbae Lee

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.

公开(公告)号：US09171755B2

公开(公告)日：2015-10-27

申请号：US14453310

申请日：2014-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Jongmin Baek ,  Dohyoung Kim ,  Tsukasa Matsuda ,  Youngwoo Cho ,  Jongseo Hong

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/764 ,  H01L21/762

CPC classification number: H01L21/7682 ,  H01L21/02296 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76885

Abstract: A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

Abstract translation: 制造半导体器件的方法可以包括：在衬底上形成具有开口的层间绝缘层; 在开口和层间绝缘层上形成金属层，金属层包括在每个开口的侧壁上的侧壁部分和在每个开口的底表面上的底部，其中底部部分比 侧壁部分; 回流金属层以在开口中形成金属图案，金属图案具有位于层间绝缘层的最上表面以下的顶表面; 和/或形成覆盖开口中的金属图案的覆盖图案。

公开(公告)号：US12021027B2

公开(公告)日：2024-06-25

申请号：US17515954

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Wandon Kim

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877

Abstract: An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.

公开(公告)号：US20240297072A1

公开(公告)日：2024-09-05

申请号：US18662083

申请日：2024-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonseok SEO ,  Euibok Lee ,  Taeyong Bae

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/32139 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266

Abstract: A a method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.

公开(公告)号：US12014951B2

公开(公告)日：2024-06-18

申请号：US17390035

申请日：2021-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoonseok Seo ,  Euibok Lee ,  Taeyong Bae

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/32139 ,  H01L21/76832 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53266

Abstract: A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1st intermetal dielectric layer; forming a 1st hardmask layer and at least one 1st photoresist pattern on the 1st intermetal dielectric layer; patterning at least one via hole penetrating through the 1st hardmask layer and the 1st intermetal dielectric using the 1st photoresist pattern; removing the 1st photoresist pattern among the 1st photoresist pattern and the 1st hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1st hardmask layer; patterning the metal structure to form at least one 1st trench penetrating at least the metal structure at a portion where the metal structure extends on the 1st hardmask layer; and filling the 1st trench with a 2nd inter-metal layer.

公开(公告)号：US20230011088A1

公开(公告)日：2023-01-12

申请号：US17705343

申请日：2022-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Rakhwan Kim ,  Wandon Kim ,  Sunyoung Noh ,  Hanmin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

公开(公告)号：US11488864B2

公开(公告)日：2022-11-01

申请号：US17150557

申请日：2021-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taeyong Bae ,  Hoonseok Seo ,  Euibok Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and a 1st via structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, a 1st vertical side of the 1st via structure does not contact a barrier metal pattern while a 2nd vertical side of the 1st via structure opposite to the 1st vertical side of the 1st via structure contacts the barrier metal pattern.