公开(公告)号：US11374001B2

公开(公告)日：2022-06-28

申请号：US16851476

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US11929366B2

公开(公告)日：2024-03-12

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0673

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20230011088A1

公开(公告)日：2023-01-12

申请号：US17705343

申请日：2022-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euibok Lee ,  Rakhwan Kim ,  Wandon Kim ,  Sunyoung Noh ,  Hanmin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.