公开(公告)号：US20140264817A1

公开(公告)日：2014-09-18

申请号：US13801675

申请日：2013-03-13

Applicant: STATS CHIPPAC, LTD.

Inventor： KyungHoon Lee ,  SangMi Park ,  KyoungIl Huh ,  DaeSik Choi

IPC: H01L23/34 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49822 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.

Abstract translation: 半导体器件包括包括多个第一半导体管芯的半导体晶片。 部分地通过半导体晶片形成开口。 多个第二半导体管芯设置在半导体晶片的第一表面上。 密封剂设置在半导体晶片上并进入开口，留下暴露的半导体晶片的第二表面。 去除半导体晶片的第二表面的一部分以分离第一半导体管芯。 在第二半导体管芯和密封剂上形成互连结构。 热界面材料沉积在第一半导体管芯的第二表面上。 散热器布置在热界面材料的上方。 在半导体晶片的第一表面上形成绝缘层。 在第一半导体管芯周围形成垂直互连结构。 导电孔通过第一半导体管芯形成。

公开(公告)号：US10068877B2

公开(公告)日：2018-09-04

申请号：US15088349

申请日：2016-04-01

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  HyunJin Song ,  Kyoungll Huh ,  DaeSik Choi

IPC: H01L21/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.

公开(公告)号：US09478486B2

公开(公告)日：2016-10-25

申请号：US14267777

申请日：2014-05-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Sun Mi Kim ,  OhHan Kim ,  KyungHoon Lee

IPC: H01L25/00 ,  H01L23/498 ,  H01L21/683 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/03 ,  H01L25/16 ,  H01L23/50 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract translation: 半导体器件具有带有硅通孔（TSV）的核心半导体器件。 核心半导体器件包括多个堆叠的半导体管芯和半导体部件。 在芯半导体器件周围形成绝缘层。 通过绝缘层形成导电通孔。 在芯半导体器件的第一侧上形成第一互连结构。 第一互连结构电连接到TSV。 在芯半导体器件的第二侧上形成第二互连结构。 第二互连结构电连接到TSV。 第一和第二互连结构包括由绝缘层分开的多个导电层。 半导体管芯安装到第一互连结构。 半导体管芯通过第一和第二互连结构和TSV电连接到芯半导体器件。

公开(公告)号：US09117812B2

公开(公告)日：2015-08-25

申请号：US14138382

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC: H01L21/4763 ,  H01L23/12 ,  H01L23/498 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US09030030B2

公开(公告)日：2015-05-12

申请号：US13760187

申请日：2013-02-06

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  KiYoun Jang ,  JoonDong Kim

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/13 ,  H01L23/31 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/50 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.

Abstract translation: 半导体器件具有安装到衬底内部的管芯附着区域的倒装芯片或PoP半导体管芯。 基板在芯片附着区域周围具有接触焊盘区域以及管芯附着区域和接触焊盘区域之间的流动控制区域。 第一通道形成在流动控制区域内的基板的表面中。 第一通道围绕芯片附接区域的周边延伸。 在流动控制区域内与第一通道相邻地形成第一坝材料。 在模具和衬底之间沉积底部填充材料。 第一通道和第一坝材料控制底部填充材料的向外流动，以防止多余的底部填充材料覆盖接触垫区域。 可以与第一坝材料相邻地形成第二通道。 可以在第一通道附近形成第二坝材料。

公开(公告)号：US20140239509A1

公开(公告)日：2014-08-28

申请号：US14267777

申请日：2014-05-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Sun Mi Kim ,  OhHan Kim ,  KyungHoon Lee

IPC: H01L23/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract translation: 半导体器件具有带有硅通孔（TSV）的核心半导体器件。 核心半导体器件包括多个堆叠的半导体管芯和半导体部件。 在芯半导体器件周围形成绝缘层。 通过绝缘层形成导电通孔。 在芯半导体器件的第一侧上形成第一互连结构。 第一互连结构电连接到TSV。 在芯半导体器件的第二侧上形成第二互连结构。 第二互连结构电连接到TSV。 第一和第二互连结构包括由绝缘层分开的多个导电层。 半导体管芯安装到第一互连结构。 半导体管芯通过第一和第二互连结构和TSV电连接到芯半导体器件。

公开(公告)号：US20140103503A1

公开(公告)日：2014-04-17

申请号：US14138382

申请日：2013-12-23

Applicant: STATS ChipPAC, Ltd.

Inventor： JaeHyun Lee ,  KiYoun Jang ,  KyungHoon Lee ,  TaeWoo Lee

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/4814 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76838 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a substrate and first conductive layer formed over the substrate. An insulating layer is formed over the first substrate with an opening over the first conductive layer. A second conductive layer is formed within the opening of the insulating layer. A portion of the second conductive layer is removed to expose a horizontal surface and side surfaces of the second conductive layer below a surface of the insulating layer. The second conductive layer has non-linear surfaces to extend a contact area of the second conductive layer. The horizontal surface and side surfaces can be stepped surfaces or formed as a ring. A third conductive layer is formed over the second conductive layer. A plurality of bumps is formed over the horizontal surface and side surfaces of the second conductive layer. A semiconductor die is mounted to the substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电层。 绝缘层在第一基板的上方形成有第一导电层上的开口。 第二导电层形成在绝缘层的开口内。 去除第二导电层的一部分以暴露第二导电层在绝缘层的表面下方的水平表面和侧表面。 第二导电层具有非线性表面以延伸第二导电层的接触面积。 水平表面和侧表面可以是台阶表面或形成为环形。 在第二导电层上形成第三导电层。 在第二导电层的水平表面和侧表面上形成多个凸块。 将半导体管芯安装到基板上。

公开(公告)号：US20130175701A1

公开(公告)日：2013-07-11

申请号：US13720516

申请日：2012-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： SeongWon Park ,  KiYoun Jang ,  KyungHoon Lee ,  JaeHyun Lee

IPC: H01L21/66 ,  H01L23/31

CPC classification number: H01L22/12 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。