公开(公告)号：US20160218089A1

公开(公告)日：2016-07-28

申请号：US15088349

申请日：2016-04-01

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  HyunJin Song ,  KyoungIl Huh ,  DaeSik Choi

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 在密封剂和半导体管芯的第一表面之上形成绝缘层。 半导体元件设置在半导体管芯的绝缘层和第一表面之上。 第一互连结构形成在半导体管芯的密封剂和第一表面上以嵌入半导体部件。 在半导体管芯中形成导电通孔。 在半导体管芯上形成散热器。 第二互连结构形成在与第一表面相对的半导体管芯的第二表面上。 在半导体部件上形成导电层。 在绝缘层中形成开口。

公开(公告)号：US09349616B2

公开(公告)日：2016-05-24

申请号：US13801294

申请日：2013-03-13

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  HyunJin Song ,  Kyoungll Huh ,  DaeSik Choi

IPC: H01L23/02 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 在密封剂和半导体管芯的第一表面之上形成绝缘层。 半导体元件设置在半导体管芯的绝缘层和第一表面之上。 第一互连结构形成在半导体管芯的密封剂和第一表面上以嵌入半导体部件。 在半导体管芯中形成导电通孔。 在半导体管芯上形成散热器。 第二互连结构形成在与第一表面相对的半导体管芯的第二表面上。 在半导体部件上形成导电层。 在绝缘层中形成开口。

公开(公告)号：US20140264905A1

公开(公告)日：2014-09-18

申请号：US13801294

申请日：2013-03-13

Applicant: STATS CHIPPAC, LTD.

Inventor： KyungHoon Lee ,  HyunJin Song ,  KyoungIl Huh ,  DaeSik Choi

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. An insulating layer is formed over the encapsulant and a first surface of the semiconductor die. A semiconductor component is disposed over the insulating layer and first surface of the semiconductor die. A first interconnect structure is formed over the encapsulant and first surface of the semiconductor die to embed the semiconductor component. A conductive via is formed in the semiconductor die. A heat sink is formed over the semiconductor die. A second interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the semiconductor component. An opening is formed in the insulating layer.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 在密封剂和半导体管芯的第一表面之上形成绝缘层。 半导体元件设置在半导体管芯的绝缘层和第一表面之上。 第一互连结构形成在半导体管芯的密封剂和第一表面上以嵌入半导体部件。 在半导体管芯中形成导电通孔。 在半导体管芯上形成散热器。 第二互连结构形成在与第一表面相对的半导体管芯的第二表面上。 在半导体部件上形成导电层。 在绝缘层中形成开口。

公开(公告)号：US20130241039A1

公开(公告)日：2013-09-19

申请号：US13871157

申请日：2013-04-26

Applicant: STATS CHIPPAC, LTD.

Inventor： DaeSik Choi ,  Sang Mi Park ,  KyungHoon Lee

IPC: H01L21/56 ,  H01L21/50 ,  H01L23/34

CPC classification number: H01L21/56 ,  H01L21/50 ,  H01L23/10 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/92225 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

Abstract translation: 半导体器件具有插入件，其内部具有管芯附着区域，并且在管芯附着区域外部具有覆盖附着区域。 通道形成在盖附接区域内的插入件的表面中。 在插入器的通道和边缘之间的覆盖附着区域内的中介层的表面上形成坝体材料。 将半导体管芯安装到插入件的管芯附着区域。 粘合剂材料沉积在覆盖物附着区域中，远离通道和坝体材料。 诸如散热器或屏蔽层的盖子被安装到盖子附接区域内的模具和插入件上。 盖子将粘合剂材料压入通道并抵靠坝体材料以控制粘合剂材料的向外流动。 或者，ACF可以形成在插入件上方以安装盖。

公开(公告)号：US09378983B2

公开(公告)日：2016-06-28

申请号：US13871157

申请日：2013-04-26

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  Sang Mi Park ,  KyungHoon Lee

IPC: H01L21/56 ,  H01L21/50 ,  H01L23/34 ,  H01L23/552 ,  H01L23/10 ,  H01L23/36 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/50 ,  H01L23/10 ,  H01L23/34 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/92225 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has an interposer with a die attach area interior to the interposer and cover attach area outside the die attach area. A channel is formed into a surface of the interposer within the cover attach area. A dam material is formed over the surface of the interposer within the cover attach area between the channel and edge of the interposer. A semiconductor die is mounted to the die attach area of the interposer. An adhesive material is deposited in the cover attach area away from the channel and dam material. A cover, such as a heat spreader or shielding layer, is mounted to the die and interposer within the cover attach area. The cover presses the adhesive material into the channel and against the dam material to control outward flow of the adhesive material. Alternatively, ACF can be formed over the interposer to mount the cover.

公开(公告)号：US20160148882A1

公开(公告)日：2016-05-26

申请号：US15011311

申请日：2016-01-29

Applicant: STATS ChipPAC, Ltd.

Inventor： OhHan Kim ,  SunMi Kim ,  KyungHoon Lee

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/563 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract translation: 半导体器件包括多层衬底。 接地屏蔽层设置在基板的层之间并且电连接到接地点。 多个半导体管芯通过接地屏蔽件安装到衬底上。 接地护罩延伸超过多个半导体管芯的覆盖区。 在多个半导体管芯和衬底上形成密封剂。 切割通道形成在密封剂中，在多个半导体管芯之间，并在接地屏蔽层之上。 沿着切割通道形成多个金属填充的孔，并延伸到基板中并通过接地屏蔽。 在多个半导体管芯上形成顶部屏蔽，并通过金属填充的孔电连接和机械地连接到接地屏蔽层。 顶部和接地屏蔽被配置为阻止相对于设置在半导体管芯中的集成无源器件产生的电磁干扰。

公开(公告)号：US09460972B2

公开(公告)日：2016-10-04

申请号：US13720516

申请日：2012-12-19

Applicant: STATS ChipPAC, Ltd.

Inventor： SeongWon Park ,  KiYoun Jang ,  KyungHoon Lee ,  JaeHyun Lee

IPC: H01L21/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。

公开(公告)号：US20130147065A1

公开(公告)日：2013-06-13

申请号：US13760187

申请日：2013-02-06

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  KiYoun Jang ,  JoonDong Kim

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/49811 ,  H01L21/50 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel.

Abstract translation: 半导体器件具有安装到衬底内部的管芯附着区域的倒装芯片或PoP半导体管芯。 基板在芯片附着区域周围具有接触焊盘区域以及管芯附着区域和接触焊盘区域之间的流动控制区域。 第一通道形成在流动控制区域内的基板的表面中。 第一通道围绕芯片附接区域的周边延伸。 在流动控制区域内与第一通道相邻地形成第一坝材料。 在模具和衬底之间沉积底部填充材料。 第一通道和第一坝材料控制底部填充材料的向外流动，以防止多余的底部填充材料覆盖接触垫区域。 可以与第一坝材料相邻地形成第二通道。 可以在第一通道附近形成第二坝材料。

公开(公告)号：US09799590B2

公开(公告)日：2017-10-24

申请号：US13801675

申请日：2013-03-13

Applicant: STATS ChipPAC, Ltd.

Inventor： KyungHoon Lee ,  SangMi Park ,  KyoungIl Huh ,  DaeSik Choi

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/498 ,  H01L21/56 ,  H01L23/36 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49822 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81

Abstract: A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.

公开(公告)号：US09543258B2

公开(公告)日：2017-01-10

申请号：US15011311

申请日：2016-01-29

Applicant: STATS ChipPAC, Ltd.

Inventor： OhHan Kim ,  SunMi Kim ,  KyungHoon Lee

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/563 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract translation: 半导体器件包括多层衬底。 接地屏蔽层设置在基板的层之间并且电连接到接地点。 多个半导体管芯通过接地屏蔽件安装到衬底上。 接地护罩延伸超过多个半导体管芯的覆盖区。 在多个半导体管芯和衬底上形成密封剂。 切割通道形成在密封剂中，在多个半导体管芯之间，并在接地屏蔽层之上。 沿着切割通道形成多个金属填充的孔，并延伸到基板中并通过接地屏蔽。 在多个半导体管芯上形成顶部屏蔽，并通过金属填充的孔电连接和机械地连接到接地屏蔽层。 顶部和接地屏蔽被配置为阻止相对于设置在半导体管芯中的集成无源器件产生的电磁干扰。