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1.发明授权Semiconductor device and method of forming reduced surface roughness in molded underfill for improved C-SAM inspection 有权半导体装置和在模塑底部填充物中形成减小的表面粗糙度的方法，以改进C-SAM检查公开(公告)号：US09460972B2
公开(公告)日：2016-10-04
申请号：US13720516
申请日：2012-12-19
Applicant: STATS ChipPAC, Ltd.
Inventor： SeongWon Park , KiYoun Jang , KyungHoon Lee , JaeHyun Lee
CPC classification number: H01L22/12 , H01L21/561 , H01L21/566 , H01L21/568 , H01L23/31 , H01L23/3128 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2224/81 , H01L2924/00 , H01L2924/00012
Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.
Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。
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2.发明申请Semiconductor Device and Method of Forming Reduced Surface Roughness in Molded Underfill for Improved C-SAM Inspection 有权半导体器件和成型底层填料中表面粗糙度降低的改进C-SAM检测方法公开(公告)号：US20130175701A1
公开(公告)日：2013-07-11
申请号：US13720516
申请日：2012-12-19
Applicant: STATS ChipPAC, Ltd.
Inventor： SeongWon Park , KiYoun Jang , KyungHoon Lee , JaeHyun Lee
CPC classification number: H01L22/12 , H01L21/561 , H01L21/566 , H01L21/568 , H01L23/31 , H01L23/3128 , H01L24/97 , H01L2224/16225 , H01L2224/97 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2224/81 , H01L2924/00 , H01L2924/00012
Abstract: A semiconductor device includes a semiconductor die. An interconnect structure is formed over an active surface of the semiconductor die. An encapsulant is formed over the semiconductor die and interconnect structure including a first surface opposite the interconnect structure. A peripheral portion of the first surface includes a first roughness disposed outside a footprint of the semiconductor die. A semiconductor die portion of the first surface includes a second roughness less than the first roughness disposed over the footprint of the semiconductor die. The first surface of the encapsulant is disposed within a mold and around the semiconductor die to contact a surface of the mold that includes a third roughness equal to the first roughness and a fourth roughness equal to the second roughness. The first roughness includes a roughness of less than 1.0 micrometers. The second roughness includes a roughness in a range of 1.2-1.8 micrometers.
Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯的有源表面上形成互连结构。 在半导体管芯和互连结构之上形成密封剂，其包括与互连结构相对的第一表面。 第一表面的周边部分包括设置在半导体管芯的占位面外的第一粗糙度。 第一表面的半导体管芯部分包括小于半导体管芯的覆盖区上的第一粗糙度的第二粗糙度。 密封剂的第一表面设置在模具内并且围绕半导体管芯接触模具的表面，该表面包括等于第一粗糙度的第三粗糙度和等于第二粗糙度的第四粗糙度。 第一粗糙度包括小于1.0微米的粗糙度。 第二粗糙度包括在1.2-1.8微米范围内的粗糙度。
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