Abstract:
An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.
Abstract:
One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.
Abstract:
Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.
Abstract:
An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.
Abstract:
An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.
Abstract:
An integrated circuit (IC) module with a lead frame micro-needle for a medical device, and methods of forming the IC module are described. The methods include forming a lead frame blank including a micro-needle integrally formed therein. The micro-needle may be bent beyond an initial lower side of the lead frame blank. The initial lower side may be joined with a protection layer such that the bent micro-needle is embedded in the protection layer, which may be removably attached to the initial lower side and the bent micro-needle. An IC component may be affixed to an upper side of the lead frame blank. The IC component and an upper surface of a core of the lead frame blank may be encapsulated with a molding compound forming a packaging of the IC module. Removal of the protection layer may expose the bent micro-needle projecting away from the packaging.
Abstract:
A system includes a first connector coupled to a first surface of a substrate. The first connector enables the system to be electrically coupled to a first device external to the substrate. The system includes a second connector coupled to a second surface of the substrate. The system also includes a plurality of conductive vias extending through the substrate from the first surface to the second surface. The plurality of conductive vias surrounds the first connector and the second connector. The plurality of conductive vias is electrically coupled together to form a toroidal inductor. A first lead of the toroidal inductor is electrically coupled to the first connector. A second lead of the toroidal inductor is electrically coupled to the second connector.
Abstract:
Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.
Abstract:
A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.
Abstract:
A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.