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    NON-VOLATILE ONE-TIME PROGRAMMABLE MEMORY DEVICE
    16.
    发明申请
    NON-VOLATILE ONE-TIME PROGRAMMABLE MEMORY DEVICE 有权
    非易失性一次可编程存储器件

    公开(公告)号：US20160020220A1

    公开(公告)日：2016-01-21

    申请号：US14495507

    申请日：2014-09-24

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Bin Yang ,  Jun Yuan ,  Xiaonan Chen ,  Zhongze Wang

    IPC: H01L27/115 ,  G11C16/10 ,  G11C16/26 ,  H01L29/792

    CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517

    Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

    Abstract translation: 一种装置包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物层。 氧化物层包括与金属栅极接触的氧化铪层和与衬底材料接触并与氧化铪层接触的二氧化硅层。 金属栅极，衬底材料和氧化物层包括在一次性可编程（OTP）存储器件中。 OTP存储器件包括晶体管。 OTP存储器件的非易失性状态基于OTP存储器件的阈值电压偏移。

    Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs)
    17.
    发明授权
    Forming self-aligned vertical interconnect accesses (VIAs) in interconnect structures for integrated circuits (ICs) 有权

    公开(公告)号：US10354912B2

    公开(公告)日：2019-07-16

    申请号：US15229535

    申请日：2016-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao Xu ,  John Jianhong Zhu ,  Choh Fei Yeap

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/498

    Abstract: Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid misalignment of a via to an underlying, interconnected metal line, vias are fabricated in the interconnect structure to be self-aligned with an underlying, interconnected metal line. In this regard, underlying metal lines are formed in a dielectric layer. A recess is formed in an underlying metal line below a top surface of an inter-layer dielectric. A stop layer is disposed above the inter-layer dielectric and within the recess of the underlying metal line. The stop layer allows a via tunnel to be formed (e.g., etched) down within the recess of the underlying metal line to self-align the via tunnel with the underlying metal line. A conductive material is then deposited in the via tunnel extending into the recess to form the self-aligned via interconnected to the underlying metal line.

    Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods
    19.
    发明授权
    Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods 有权

    公开(公告)号：US10115723B2

    公开(公告)日：2018-10-30

    申请号：US15602326

    申请日：2017-05-23

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao Xu

    IPC: H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238

    Abstract: Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods are disclosed. In certain aspects, a source and drain of a CMOS device are formed at end portions of a channel structure by plasma doping end portions of the channel structure above solid state solubility of the channel structure, and annealing the end portions for liquid phase epitaxy and activation (e.g., superactivation). In this manner, the source and drain can be integrally formed in the end portions of the channel structure to provide coextensive surface area contact between the source and drain and the channel structure for lower channel contact resistance. This is opposed to forming the source/drain using epitaxial growth that provides an overgrowth beyond the end portion surface area of the channel structure to reduce channel contact resistance, which may short adjacent channels structures.

    Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
    20.
    发明授权
    Standard cell circuits employing high aspect ratio voltage rails for reduced resistance 有权

    公开(公告)号：US10090244B2

    公开(公告)日：2018-10-02

    申请号：US15634039

    申请日：2017-06-27

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Junhao Xu ,  Mustafa Badaroglu ,  Da Yang ,  Periannan Chidambaram

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L27/02 ,  G06F17/50 ,  H01L27/118

    Abstract: Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

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