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    MULTI-STEP PROGRAMMING OF HEAT-SENSITIVE NON-VOLATILE MEMORY (NVM) IN PROCESSOR-BASED SYSTEMS
    14.
    发明申请
    MULTI-STEP PROGRAMMING OF HEAT-SENSITIVE NON-VOLATILE MEMORY (NVM) IN PROCESSOR-BASED SYSTEMS 有权
    基于处理器的系统中的高可靠性非易失性存储器（NVM）的多级编程

    公开(公告)号：US20160246608A1

    公开(公告)日：2016-08-25

    申请号：US14627318

    申请日：2015-02-20

    Applicant: QUALCOMM Incorporated

    Inventor： Adam Edward Newham ,  Rashid Ahmed Akbar Attar ,  Seung Hyuk Kang ,  Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

    IPC: G06F9/44 ,  G06F13/28 ,  G06F12/02

    CPC classification number: G06F13/28 ,  G06F9/4406 ,  G06F12/0246 ,  G06F2212/7209

    Abstract: Multi-step programming of heat-sensitive non-volatile memory (NVM) in processor-based systems, and related methods and systems are disclosed. To avoid relying on programmed instructions stored in heat-sensitive NVM during fabrication, wherein the programmed instructions can become corrupted during thermal packaging processes, the NVM is programmed in a multi-step programming process. In a first programming step, a boot loader comprising programming instructions is loaded into the NVM. The boot loader may be loaded into the NVM after the thermal processes during packaging are completed to avoid risking data corruption in the boot loader. Thereafter, the programmed image can be loaded quickly into a NV program memory over the peripheral interface using the boot loader to save programming time and associated costs, as opposed to loading the programmed image using lower transfer rate programming techniques. The processor can execute the program instructions to carry out tasks in the processor-based system.

    Abstract translation: 公开了基于处理器的系统中的热敏非易失性存储器（NVM）的多步编程以及相关的方法和系统。 为了避免在制造期间依赖于存储在热敏NVM中的编程指令，其中编程指令可能在热封装过程中被破坏，NVM以多步编程过程编程。 在第一编程步骤中，包括编程指令的引导加载器被加载到NVM中。 引导加载程序可能在打包完成后的热处理后加载到NVM中，以避免引导加载程序中的数据损坏风险。 此后，与使用较低传输速率编程技术加载编程图像相比，编程图像可以使用引导加载程序通过外设接口快速加载到NV程序存储器中，从而节省编程时间和相关成本。 处理器可以执行程序指令以在基于处理器的系统中执行任务。

    Sense amplifier offset voltage reduction
    16.
    发明授权
    Sense amplifier offset voltage reduction 有权
    感应放大器失调电压降低

    公开(公告)号：US09140747B2

    公开(公告)日：2015-09-22

    申请号：US13947144

    申请日：2013-07-22

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Daeik D. Kim

    IPC: G11C7/00 ,  G01R31/28 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46 ,  G11C16/28 ,  G11C29/02

    CPC classification number: G01R31/2851 ,  G11C16/28 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C29/14 ,  G11C29/44 ,  G11C29/46

    Abstract: A circuit includes a plurality of transistors responsive to a plurality of latches that store a test code. The circuit further includes a first bit line coupled to a data cell and coupled to a sense amplifier. The circuit also includes a second bit line coupled to a reference cell and coupled to the sense amplifier. A current from a set of the plurality of transistors is applied to the data cell via the first bit line. The set of the plurality of transistors is determined based on the test code. The circuit also includes a test mode reference circuit coupled to the first bit line and to the second bit line.

    Abstract translation: 电路包括响应于存储测试码的多个锁存器的多个晶体管。 电路还包括耦合到数据单元并耦合到读出放大器的第一位线。 电路还包括耦合到参考单元并耦合到读出放大器的第二位线。 来自一组多个晶体管的电流经由第一位线被施加到数据单元。 基于测试代码来确定多个晶体管的集合。 电路还包括耦合到第一位线和第二位线的测试模式参考电路。

    Write pulse width scheme in a resistive memory
    17.
    发明授权
    Write pulse width scheme in a resistive memory 有权
    在电阻性存储器中写入脉冲宽度方案

    公开(公告)号：US09135975B2

    公开(公告)日：2015-09-15

    申请号：US14064959

    申请日：2013-10-28

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Jung Pill Kim ,  Sungryul Kim

    IPC: G11C11/16 ,  G11C29/54 ,  G11C13/00 ,  G11C29/02 ,  G11C29/24

    CPC classification number: G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C29/24 ,  G11C2013/0083 ,  G11C2013/0092

    Abstract: A resistive memory array includes a controller, a test reset driver coupled to the controller, a test write driver also coupled to the controller, and a test read sense amplifier also coupled to the controller. The resistive memory array also includes a set of test resistive memory elements representing a resistive memory macro. The test resistive memory elements are coupled to the test reset driver, the test write driver and the test read sense amplifier. A change in the state of one of the test resistive memory elements represents a change in the state of a set of corresponding elements in the resistive memory macro.

    Abstract translation: 电阻性存储器阵列包括控制器，耦合到控制器的测试复位驱动器，还耦合到控制器的测试写入驱动器，以及还耦合到控制器的测试读取读出放大器。 电阻存储器阵列还包括表示电阻存储器宏的一组测试电阻存储器元件。 测试电阻存储元件耦合到测试复位驱动器，测试写驱动器和测试读读放大器。 一个测试电阻存储器元件的状态的变化表示电阻存储器宏中一组相应元件的状态的变化。

    Memory cell array with reserved sector for storing configuration information
    18.
    发明授权
    Memory cell array with reserved sector for storing configuration information 有权
    具有保留扇区的存储单元阵列用于存储配置信息

    公开(公告)号：US08913450B2

    公开(公告)日：2014-12-16

    申请号：US13680361

    申请日：2012-11-19

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim

    IPC: G11C7/00 ,  G11C7/20 ,  G11C16/20 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C7/20 ,  G11C16/20 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

    Abstract: A memory device is provided including a cell array and a volatile storage device. The cell array may include a plurality of word lines, a plurality of bit lines, wherein a selection of a word line and bit line defines a memory cell address, and a non-volatile reserved word line for storing configuration information for the cell array. The volatile storage device is coupled to the cell array. The configuration information from the non-volatile reserved word line is copied to the volatile storage device upon power-up or initialization of the memory device.

    Abstract translation: 提供了包括单元阵列和易失性存储装置的存储装置。 单元阵列可以包括多个字线，多个位线，其中字线和位线的选择定义存储器单元地址，以及用于存储单元阵列的配置信息的非易失性保留字线。 易失性存储设备耦合到单元阵列。 来自非易失性保留字线的配置信息在上电或初始化存储器件时被复制到易失性存储设备。

    System and method of reference cell testing
    19.
    发明授权
    System and method of reference cell testing 失效
    参考细胞测试的系统和方法

    公开(公告)号：US08787098B2

    公开(公告)日：2014-07-22

    申请号：US13778173

    申请日：2013-02-27

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Hari M. Rao

    IPC: G11C5/14

    CPC classification number: G11C7/062 ,  G06F17/50 ,  G11C11/16 ,  G11C29/24

    Abstract: Systems and methods of testing a reference cell in a memory array are disclosed. In a particular embodiment, a method includes coupling a first reference cell of a first reference cell pair of a memory array to a first input of a first sense amplifier of the memory array. The method also includes providing a reference signal to a second input of the first sense amplifier. The reference signal is associated with a second reference cell pair of the memory array.

    Abstract translation: 公开了测试存储器阵列中的参考单元的系统和方法。 在特定实施例中，一种方法包括将存储器阵列的第一参考单元对的第一参考单元耦合到存储器阵列的第一读出放大器的第一输入。 该方法还包括向第一读出放大器的第二输入提供参考信号。 参考信号与存储器阵列的第二参考单元对相关联。

    MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR
    20.
    发明申请
    MAGNETIC TUNNEL JUNCTION BASED RANDOM NUMBER GENERATOR 审中-公开
    基于磁性隧道结的随机数发生器

    公开(公告)号：US20140108478A1

    公开(公告)日：2014-04-17

    申请号：US13651954

    申请日：2012-10-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kangho Lee ,  Taehyun Kim ,  Xiaochun Zhu ,  David M. Jacobson ,  Raghu Sagar Madala ,  Wenqing Wu ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G06F7/58

    CPC classification number: G06F7/588

    Abstract: A random number generator system that utilizes a magnetic tunnel junction (MTJ) that is controlled by an STT-MTJ entropy controller that determines whether to proceed with generating random numbers or not by monitoring the health of the MTJ-based random number generator is illustrated. If the health of the random number generation is above a threshold, the STT-MTJ entropy controller shuts down the MTJ-based random number generator and sends a message to a requesting chipset that a secure key generation is not possible. If the health of the random number generation is below a threshold, the entropy controller allows the MTJ-based random number generator to generate random numbers based on a specified algorithm, the output of which is post processed and used by a cryptographic-quality deterministic random bit generator to generate a security key for a requesting chipset.

    Abstract translation: 示出了利用由STT-MTJ熵控制器控制的磁隧道结（MTJ）的随机数发生器系统，其通过监测基于MTJ的随机数发生器的健康来确定是否继续生成随机数。 如果随机数生成的健康状况高于阈值，则STT-MTJ熵控制器关闭基于MTJ的随机数生成器，并且向请求芯片组发送消息，即不可能产生安全密钥。 如果随机数生成的健康状况低于阈值，则熵控制器允许基于MTJ的随机数发生器基于指定的算法产生随机数，其输出被后处理并由加密质量确定性随机使用 以产生请求芯片组的安全密钥。

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