Abstract:
A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.
Abstract:
A magnetic tunnel junction (MTJ) device includes a free layer. The MTJ also includes a barrier layer coupled to the free layer. The MTJ also has a fixed layer, coupled to the barrier layer. The fixed layer includes a first synthetic antiferromagnetic (SAF) multilayer having a first perpendicular magnetic anisotropy (PMA) and a first damping constant. The fixed layer also includes a second SAF multilayer having a second perpendicular magnetic anisotropy (PMA) and a second damping constant lower than the first damping constant. The first SAF multilayer is closer to the barrier layer than the second SAF multilayer. The fixed layer also includes a SAF coupling layer between the first and the second SAF multilayers.
Abstract:
Methods and apparatus relating to spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy are disclosed. In an example, disclosed is a three-terminal magnetic tunnel junction (MTJ) storage element that is programmed via a combination of voltage-controlled magnetic anisotropy (VCMA) and spin-orbit torque (SOT) techniques. Also disclosed is a memory controller configured to program the three-terminal MTJ storage element via VCMA and SOT techniques. The disclosed devices improve efficiency over conventional devices by using less write energy, while having a design that is simpler and more scalable than conventional devices. The disclosed devices also have increased thermal stability without increasing required switching current, as critical switching current between states is essentially the same.
Abstract:
A memory cell includes a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.
Abstract:
In a particular embodiment, a method includes controlling a temperature within a chamber while applying a magnetic field. A device including a memory array is located in the chamber. The method includes applying a magnetic field to the memory array and testing the memory array during application of the magnetic field to the memory array at a target temperature.
Abstract:
One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.
Abstract:
One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.
Abstract:
A magnetic tunnel junction device includes a Synthetic Anti-Ferromagnetic (SAF) layer, a first free layer, and second free layer. The magnetic tunnel junction device further includes a spacer layer between the first and second free layers. The first free layer is magneto-statically coupled to the second free layer. A thickness of the spacer layer is at least 4 Angstroms.
Abstract:
A memory device includes a magnetic tunnel junction (MTJ) bitcell. The MTJ bitcell includes a first MTJ and a second MTJ. The memory device further includes programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell. The non-reversible state corresponds to a value of the MTJ bitcell that is determined by comparing a first value read at the first MTJ and a second value read at the second MTJ.
Abstract:
Several novel features pertain to an automatic testing equipment (ATE) memory tester that includes a load board, a projected-field electromagnet, a positioning mechanism and a memory tester. The load board is for coupling to a die package that includes a magnetoresistive random access memory (MRAM) having several cells, where each cell includes a magnetic tunnel junction (MTJ). The projected-field electromagnet is for applying a portion of a magnetic field across the MRAM. The portion of the magnetic field may be substantially uniform. The positioning mechanism is coupled to the electromagnet and the load board, and is configured to position the electromagnet vertically about (above/below) the die package when the die package is coupled to the load board. The memory tester is coupled to the load board. The memory tester is for testing the MRAM when the substantially uniform portion of the magnetic field is applied across the MRAM.