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    Data retention error detection system
    2.
    发明授权
    Data retention error detection system 有权
    数据保留错误检测系统

    公开(公告)号：US09159455B2

    公开(公告)日：2015-10-13

    申请号：US14138059

    申请日：2013-12-21

    Applicant: QUALCOMM Incorporated

    Inventor： Xiao Lu ,  Wah Nam Hsu

    IPC: G11C11/00 ,  G11C29/10 ,  G06F11/07 ,  G11C29/50 ,  G11C11/16

    CPC classification number: G11C29/10 ,  G06F11/073 ,  G11C11/16 ,  G11C29/50016

    Abstract: A particular method includes selecting a threshold data retention time of a magnetic tunnel junction (MTJ) memory cell. A pinned layer of the MTJ memory cell has a first direction of magnetization, and a free layer of the MTJ memory cell has a second direction of magnetization. An external magnetic field that has a third direction of magnetization that is opposite to the second direction of magnetization is applied to the MTJ memory cell. A strength of the external magnetic field is determined based on the threshold data retention time. Subsequent to applying the external magnetic field, a read operation is performed on the MTJ memory cell to determine a logic value of the MTJ memory cell. The method further includes determining whether the MTJ memory cell is subject to a data retention error corresponding to the threshold data retention time based on the logic value.

    Abstract translation: 一种特定方法包括选择磁性隧道结（MTJ）存储单元的阈值数据保留时间。 MTJ存储单元的钉扎层具有第一磁化方向，并且MTJ存储单元的自由层具有第二磁化方向。 具有与第二磁化方向相反的第三磁化方向的外部磁场施加到MTJ存储单元。 基于阈值数据保持时间确定外部磁场的强度。 在施加外部磁场之后，对MTJ存储单元执行读取操作以确定MTJ存储器单元的逻辑值。 该方法还包括基于逻辑值确定MTJ存储器单元是否受到与阈值数据保留时间相对应的数据保留错误。

    MAGNETIC TUNNEL JUNCTION (MTJ) ON PLANARIZED ELECTRODE
    3.
    发明申请
    MAGNETIC TUNNEL JUNCTION (MTJ) ON PLANARIZED ELECTRODE 有权
    平面电极上的磁性隧道结（MTJ）

    公开(公告)号：US20140073064A1

    公开(公告)日：2014-03-13

    申请号：US14086054

    申请日：2013-11-21

    Applicant: QUALCOMM Incorporated

    Inventor： Seung Hyuk Kang ,  Xia Li ,  Wei-Chuan Chen ,  Kangho Lee ,  Xiaochun Zhu ,  Wah Nam Hsu

    IPC: H01L43/12

    CPC classification number: H01L43/12 ,  H01L43/08

    Abstract: A magnetic tunnel junction (MTJ) with direct contact is manufactured having lower resistances, improved yield, and simpler fabrication. The lower resistances improve both read and write processes in the MTJ. The MTJ layers are deposited on a bottom electrode aligned with the bottom metal. An etch stop layer may be deposited adjacent to the bottom metal to prevent overetch of an insulator surrounding the bottom metal. The bottom electrode is planarized before deposition of the MTJ layers to provide a substantially flat surface. Additionally, an underlayer may be deposited on the bottom electrode before the MTJ layers to promote desired characteristics of the MTJ.

    Abstract translation: 具有直接接触的磁性隧道结（MTJ）被制造成具有较低的电阻，提高的产量和更简单的制造。 较低的电阻提高了MTJ中的读取和写入过程。 MTJ层沉积在与底部金属对准的底部电极上。 蚀刻停止层可以沉积在底部金属附近，以防止围绕底部金属的绝缘体的过蚀刻。 在沉积MTJ层之前将底部电极平坦化以提供基本平坦的表面。 另外，可以在MTJ层之前的底部电极上沉​​积底层以促进MTJ的期望特性。

    Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature
    4.
    发明授权
    Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature 有权

    公开(公告)号：US10431278B2

    公开(公告)日：2019-10-01

    申请号：US15676957

    申请日：2017-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

    IPC: G11C11/16 ,  G11C5/14 ,  G11C7/04 ,  G11C29/50 ,  H01L27/22 ,  H01L43/08

    Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

    DYNAMICALLY CONTROLLING VOLTAGE FOR ACCESS OPERATIONS TO MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) BIT CELLS TO ACCOUNT FOR AMBIENT TEMPERATURE
    8.
    发明申请
    DYNAMICALLY CONTROLLING VOLTAGE FOR ACCESS OPERATIONS TO MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) BIT CELLS TO ACCOUNT FOR AMBIENT TEMPERATURE 审中-公开

    公开(公告)号：US20190051341A1

    公开(公告)日：2019-02-14

    申请号：US15676957

    申请日：2017-08-14

    Applicant: QUALCOMM Incorporated

    Inventor： Xia Li ,  Wah Nam Hsu ,  Wei-Chuan Chen ,  Seung Hyuk Kang

    IPC: G11C11/16

    Abstract: Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for ambient temperature is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations and ambient temperature in magnetic tunnel junctions (MTJs) that affect MTJ resistance, which can change the write current at a given fixed supply voltage applied to an MRAM bit cell. These measured process variations and ambient temperature are used to dynamically control a supply voltage for access operations to the MRAM to reduce the likelihood of bit errors and reduce power consumption. The MRAM bit cell PVMC may also be configured to measure process variations and/or ambient temperatures in logic circuits that represent the process variations and ambient temperatures in access transistors employed in MRAM bit cells in the MRAM to determine variations in the switching speed (i.e., drive strength) of the access transistors.

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