公开(公告)号：US09437534B2

公开(公告)日：2016-09-06

申请号：US14714331

申请日：2015-05-17

申请人： MEDIATEK INC.

发明人： Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

IPC分类号： H01L23/498 ,  H01L23/00

CPC分类号： H01L23/49822 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05552

摘要： A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

摘要翻译： 倒装芯片封装包括：耦合到管芯的载体。 载体包括：用于将载体的表面耦合到载体中的电迹线的至少一个通孔; 以及至少一个电耦合到所述通孔的捕获垫，其中所述捕获垫被电镀在所述通孔上。 模具包括：至少形成在模具表面上的接合焊盘; 以及形成在所述接合焊盘上的至少一个铜柱，用于将所述管芯耦合到所述载体上的捕获垫，其中所述铜柱的一部分突出于所述通孔开口。

公开(公告)号：US11373957B2

公开(公告)日：2022-06-28

申请号：US16994764

申请日：2020-08-17

申请人： MEDIATEK Inc.

发明人： Wen-Sung Hsu ,  Tao Cheng ,  Nan-Cheng Chen ,  Che-Ya Chou ,  Wen-Chou Wu ,  Yen-Ju Lu ,  Chih-Ming Hung ,  Wei-Hsiu Hsu

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/00 ,  H01Q1/22 ,  H01Q9/04 ,  H01L23/14 ,  H01L23/00 ,  H01Q21/06

摘要： A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20210036405A1

公开(公告)日：2021-02-04

申请号：US17075561

申请日：2020-10-20

申请人： MediaTek Inc.

发明人： Fu-Yi Han ,  Che-Ya Chou ,  Che-Hung Kuo ,  Wen-Chou Wu ,  Nan-Cheng Chen ,  Min-Chen Lin ,  Hsing-Chih Liu

IPC分类号： H01Q1/22 ,  H01L23/66 ,  H01L23/498 ,  H01L23/538

摘要： One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.

公开(公告)号：US20200168572A1

公开(公告)日：2020-05-28

申请号：US16779217

申请日：2020-01-31

申请人： MediaTek Inc.

发明人： Tzu-Hung Lin ,  I-Hsuan Peng ,  Nai-Wei Liu ,  Wei-Che Huang ,  Che-Ya Chou

IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/16

摘要： The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

公开(公告)号：US10224287B2

公开(公告)日：2019-03-05

申请号：US15613144

申请日：2017-06-03

申请人： MEDIATEK INC.

发明人： Shih-Yi Syu ,  Tung-Hsien Hsieh ,  Che-Ya Chou

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H01L23/29 ,  H01L23/525

摘要： An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

公开(公告)号：US10128192B2

公开(公告)日：2018-11-13

申请号：US15498542

申请日：2017-04-27

申请人： MEDIATEK INC.

发明人： Min-Chen Lin ,  Che-Ya Chou ,  Nan-Cheng Chen

IPC分类号： H01L25/16 ,  H01L23/12 ,  H01L23/528 ,  H01L23/31 ,  H01L23/66 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00

摘要： A semiconductor package structure including a redistribution layer (RDL) structure having a first surface and a second surface opposite thereto is provided. The RDL structure includes an inter-metal dielectric (IMD) layer and a first conductive layer disposed at a first layer-level of the IMD layer. A molding compound covers the first surface of the RDL structure. A first semiconductor die is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure. A plurality of bump structures is disposed over the second surface of the RDL structure and electrically coupled to the RDL structure.

公开(公告)号：US20160276277A1

公开(公告)日：2016-09-22

申请号：US15006082

申请日：2016-01-25

申请人： MEDIATEK INC.

发明人： Shih-Yi Syu ,  Tung-Hsien Hsieh ,  Che-Ya Chou

IPC分类号： H01L23/538 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/5386 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53228 ,  H01L23/5384 ,  H01L23/66 ,  H01L24/05 ,  H01L24/09 ,  H01L24/17 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/0655 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05013 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/73209 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

摘要翻译： 钝化层上的RDL结构包括直接设置在第一片上金属焊盘上方的第一着陆焊盘; 钝化层中的第一通孔，用于将第一着陆焊盘与第一片上金属焊盘电连接; 第二着陆焊盘，其设置在所述第二片上金属焊盘的正上方; 在所述钝化层中的第二通孔，用于将所述第二着陆焊盘与所述第二片上金属焊盘电连接; 并且至少五个迹线设置在钝化层上并且穿过第一着陆焊盘和第二着陆焊盘之间的空间。

公开(公告)号：US20160005726A1

公开(公告)日：2016-01-07

申请号：US14850962

申请日：2015-09-11

申请人： MEDIATEK INC.

发明人： Nan-Cheng Chen ,  Che-Ya Chou

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/0912 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

摘要翻译： 系统级封装包括封装载体; 第一半导体管芯，其具有管芯面和管芯边缘，所述第一半导体管芯正面朝下地组装到所述封装载体的芯片侧，其中，多个接触焊盘位于所述管芯面上; 安装在所述封装载体上并与所述第一半导体管芯相邻的第二半导体管芯; 在所述第一半导体管芯和所述封装载体之间的重新布线层压结构，所述重新布线层压结构包括重新布线的金属层，其中所述重新布线的金属层的至少一部分突出超过所述管芯边缘; 以及布置在重新布线层压结构上的多个铜柱凸块，用于将第一半导体管芯与封装载体电连接。

公开(公告)号：US09165877B2

公开(公告)日：2015-10-20

申请号：US14045803

申请日：2013-10-04

申请人： MEDIATEK INC.

发明人： Nan-Cheng Chen ,  Che-Ya Chou

IPC分类号： H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/18 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/09 ,  H01L24/17 ,  H01L24/19 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0912 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/142 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

摘要翻译： 系统级封装包括封装载体; 第一半导体管芯，其具有管芯面和管芯边缘，所述第一半导体管芯正面朝下地组装到所述封装载体的芯片侧，其中，多个接触焊盘位于所述管芯面上; 安装在所述封装载体上并与所述第一半导体管芯相邻的第二半导体管芯; 在所述第一半导体管芯和所述封装载体之间的重新布线层压结构，所述重新布线层压结构包括重新布线的金属层，其中所述重新布线的金属层的至少一部分突出超过所述管芯边缘; 以及布置在重新布线层压结构上的多个铜柱凸块，用于将第一半导体管芯与封装载体电连接。

公开(公告)号：US11908759B2

公开(公告)日：2024-02-20

申请号：US17190584

申请日：2021-03-03

申请人： MediaTek Inc.

发明人： Nan-Cheng Chen ,  Che-Ya Chou ,  Hsing-Chih Liu ,  Che-Hung Kuo

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/482 ,  H01L25/04 ,  H01L23/14 ,  H01L25/18

CPC分类号： H01L23/31 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/043 ,  H01L25/0652 ,  H01L25/0655 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06541 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/157 ,  H01L2924/15311 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.