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公开(公告)号：US20150187886A1
公开(公告)日：2015-07-02
申请号：US14311675
申请日：2014-06-23
Inventor： Young Rak PARK , Sang Choon KO , Woojin CHANG , Jae Kyoung MUN , Sung-Bum BAE
IPC: H01L29/20 , H01L29/49 , H01L29/417 , H01L29/205
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66431 , H01L29/737 , H01L29/778 , H01L29/7786
Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
Abstract translation: 提供一种氮化物半导体器件，包括：具有通孔的衬底; 顺序堆叠在基板上的第一和第二氮化物半导体层; 设置在第二氮化物半导体层上的漏电极和源电极; 以及设置在所述第二氮化物半导体层上的绝缘图案，所述绝缘图案具有设置在所述漏电极上的上通孔，所述贯通通孔延伸到所述第一氮化物半导体层和所述第二氮化物半导体层中，并暴露出每个所述源电极的底部 。
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公开(公告)号：US20150187599A1
公开(公告)日：2015-07-02
申请号：US14310784
申请日：2014-06-20
Inventor： Sang Choon KO , Jae Kyoung MUN , Woojin CHANG , Sung-Bum BAE , Young Rak PARK , Chi Hoon JUN , Seok-Hwan MOON , Woo-Young JANG , Jeong-Jin KIM , Hyungyu JANG , Je Ho NA , Eun Soo NAM
IPC: H01L21/321 , H01L21/283 , H01L21/02
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。
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公开(公告)号：US20140213045A1
公开(公告)日：2014-07-31
申请号：US14230031
申请日：2014-03-31
Inventor： Sung Bum BAE , Eun Soo NAM , Jae Kyoung MUN , Sung Bock KIM , Hae Cheon KIM , Chull Won JU , Sang Choon KO , Jong-Won LIM , Ho Kyun AHN , Woo Jin CHANG , Young Rak PARK
IPC: H01L29/66
CPC classification number: H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可以通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。
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公开(公告)号：US20140159049A1
公开(公告)日：2014-06-12
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon KO , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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Patent Agency Ranking
公开(公告)号：US20170201247A1
公开(公告)日：2017-07-13
申请号：US15217271
申请日：2016-07-22
Inventor： Woojin CHANG , Sang Choon KO , Jae Kyoung MUN , Young Rak PARK
IPC: H03K17/081 , H03K17/74
CPC classification number: H03K17/08104 , H03K17/0822 , H03K17/74
Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.
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公开(公告)号：US20170117889A1
公开(公告)日：2017-04-27
申请号：US15223826
申请日：2016-07-29
Inventor： Minki KIM , Hyun-Gyu JANG , Dong Yun JUNG , Sang Choon KO , Hyun Soo LEE , Chi Hoon JUN
IPC: H03K17/081 , H01L27/088 , H01L29/20 , H01L29/778
CPC classification number: H03K17/08104 , H01L27/0883 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/778 , H01L29/7786 , H03K17/102 , H03K2017/6875
Abstract: Provided is a stabilizing circuit structure using a sense field effect transistor (sense-FET). A power semiconductor module includes a depletion-mode field effect transistor (D-mode FET) and the sense FET that has same structure as the D-mode FET and varies in area. Also the power semiconductor module includes not only an enhancement-mode field effect transistor (E-mode FET), but also the stabilizing circuit including circuit elements such as a resistor, a capacitor, an inductor, or a diode.
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公开(公告)号：US20170025550A1
公开(公告)日：2017-01-26
申请号：US15215414
申请日：2016-07-20
Inventor： Dong Yun JUNG , Hyun Soo LEE , Sang Choon KO , Minki KIM , Jeho NA , EUN SOO NAM , Young Rak PARK , Junbo PARK , Hyung Seok LEE , Hyun-Gyu JANG , Chi Hoon JUN
IPC: H01L29/861 , H01L29/205
CPC classification number: H01L29/205 , H01L29/2003 , H01L29/66212 , H01L29/872
Abstract: Provided is a bridge diode according to an embodiment of the inventive concept. The bridge diode includes a first structure including a first lower nitride film and a first upper nitride film, which are laminated on the substrate, a second structure including a second lower nitride film and a second upper nitride film, which are laminated on the substrate, a first electrode structural body disposed on the first structure, and a second electrode structural body disposed on the second structure. The first electrode structural body includes a first electrode, a second electrode, and a third electrode, which are arranged in a clockwise direction, the second electrode structural body includes a fourth electrode, a fifth electrode, and a sixth electrode, which are arranged in a clockwise direction, the first electrode and the sixth electrode, which are connected to each other, are connected to an external circuit, the third electrode and the fourth electrode, which are connected to each other, are connected to an external circuit, and each of the second electrode and the fifth electrode is connected to the external circuit.
Abstract translation: 提供根据本发明构思的实施例的桥式二极管。 桥式二极管包括层叠在基板上的第一下部氮化物膜和第一上部氮化物膜的第一结构，包括层叠在基板上的第二下部氮化物膜和第二上部氮化物膜的第二结构， 设置在第一结构上的第一电极结构体和设置在第二结构上的第二电极结构体。 第一电极结构体包括沿顺时针方向布置的第一电极，第二电极和第三电极，第二电极结构体包括第四电极，第五电极和第六电极，其布置在 连接到彼此连接的顺时针方向，第一电极和第六电极连接到彼此连接的外部电路，第三电极和第四电极连接到外部电路，并且每个 的第二电极和第五电极连接到外部电路。
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公开(公告)号：US20150194363A1
公开(公告)日：2015-07-09
申请号：US14324724
申请日：2014-07-07
Inventor： Chi Hoon JUN , Sang Choon KO , Seok-Hwan MOON , Woojin CHANG , Sung-Bum BAE , Young Rak PARK , Je Ho NA , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L23/367 , H01L21/3205 , H01L23/467 , H01L21/3065 , H01L21/308 , H01L23/473
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。
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公开(公告)号：US20140054262A1
公开(公告)日：2014-02-27
申请号：US14066085
申请日：2013-10-29
Inventor： Chi Hoon JUN , Sang Choon KO , Jong Tae MOON
IPC: H01L41/29 , H01L41/317 , H01L41/318 , H01L41/316
CPC classification number: H01L41/29 , H01L41/1136 , H01L41/31 , H01L41/316 , H01L41/317 , H01L41/318 , H02N2/188 , Y10T29/42
Abstract: Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
Abstract translation: 公开了一种压电微能量收集器及其制造方法，该方法包括：在基板上形成绝缘膜; 图案化绝缘膜并形成电极焊盘图案，中心电极图案和侧面电极图案; 在所述基板的内部形成开放空腔，以悬浮所述中心电极图案和所述侧面电极图案; 在电极焊盘图形，中心电极图案和侧面电极图案上设置导电膜，形成电极焊盘，中心电极和侧面电极; 以及形成压电膜以覆盖中心电极和侧电极之间的空间以及中心电极和侧电极的上表面。
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