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公开(公告)号：US08937002B2
公开(公告)日：2015-01-20
申请号：US14230031
申请日：2014-03-31
Inventor： Sung Bum Bae , Eun Soo Nam , Jae Kyoung Mun , Sung Bock Kim , Hae Cheon Kim , Chull Won Ju , Sang Choon Ko , Jong-Won Lim , Ho Kyun Ahn , Woo Jin Chang , Young Rak Park
IPC: H01L21/20 , H01L29/66 , H01L21/8252 , H01L27/06 , H01L27/088 , H01L21/02
CPC classification number: H01L29/66446 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L21/8252 , H01L27/0605 , H01L27/0883
Abstract: The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.
Abstract translation: 本发明涉及一种氮化物电子器件及其制造方法，特别涉及一种氮化物电子器件及其制造方法，该氮化物电子器件及其制造方法可通过再生技术在同一衬底上实现各种氮化物一体化结构（ 用于包括III族元素如镓（Ga），铝（Al）和铟（In））和氮（III）的III族氮化物半导体电子器件中的半绝缘氮化镓（GaN）层的外延横向过度生长：ELOG） 。
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公开(公告)号：US09825622B2
公开(公告)日：2017-11-21
申请号：US15217271
申请日：2016-07-22
Inventor： Woojin Chang , Sang Choon Ko , Jae Kyoung Mun , Young Rak Park
IPC: H03K17/687 , H03K17/081 , H03K17/74
CPC classification number: H03K17/08104 , H03K17/0822 , H03K17/74
Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.
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公开(公告)号：US09209266B2
公开(公告)日：2015-12-08
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won Lim , Ho Kyun Ahn , Young Rak Park , Dong Min Kang , Woo Jin Chang , Seong-il Kim , Sung Bum Bae , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/265 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/778 , H01L29/16 , H01L21/311
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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公开(公告)号：US09136396B2
公开(公告)日：2015-09-15
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon Ko , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808 , H01L29/417 , H01L29/778 , H01L29/43 , H01L29/45 , H01L29/20
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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公开(公告)号：US20140159049A1
公开(公告)日：2014-06-12
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon KO , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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Patent Agency Ranking
公开(公告)号：US10020201B2
公开(公告)日：2018-07-10
申请号：US15093814
申请日：2016-04-08
Inventor： Chi Hoon Jun , Sang Choon Ko , Seok-Hwan Moon , Woojin Chang , Sung-Bum Bae , Young Rak Park , Je Ho Na , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/367 , H01L21/3065 , H01L21/308 , H01L21/3205 , H01L23/473 , H01L23/467
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
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公开(公告)号：US09755027B2
公开(公告)日：2017-09-05
申请号：US15265647
申请日：2016-09-14
Inventor： Hyung Seok Lee , Ki Hwan Kim , Sang Choon Ko , Zin-Sig Kim , Jeho Na , Eun Soo Nam , Young Rak Park , Junbo Park , Chi hoon Jun , Dong Yun Jung
IPC: H01L29/66 , H01L29/40 , H01L29/778 , H01L29/423 , H01L29/20 , H01L29/417
CPC classification number: H01L29/402 , H01L29/2003 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66462 , H01L29/7786
Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
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公开(公告)号：US09159583B2
公开(公告)日：2015-10-13
申请号：US14310784
申请日：2014-06-20
Inventor： Sang Choon Ko , Jae Kyoung Mun , Woojin Chang , Sung-Bum Bae , Young Rak Park , Chi Hoon Jun , Seok-Hwan Moon , Woo-Young Jang , Jeong-Jin Kim , Hyungyu Jang , Je Ho Na , Eun Soo Nam
IPC: H01L21/33 , H01L21/321 , H01L21/02 , H01L21/283
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。
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公开(公告)号：US09136347B2
公开(公告)日：2015-09-15
申请号：US14311675
申请日：2014-06-23
Inventor： Young Rak Park , Sang Choon Ko , Woojin Chang , Jae Kyoung Mun , Sung-Bum Bae
IPC: H01L29/66 , H01L29/20 , H01L29/205 , H01L29/49 , H01L29/417 , H01L29/778 , H01L29/737
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66431 , H01L29/737 , H01L29/778 , H01L29/7786
Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
Abstract translation: 提供一种氮化物半导体器件，包括：具有通孔的衬底; 顺序堆叠在基板上的第一和第二氮化物半导体层; 设置在第二氮化物半导体层上的漏电极和源电极; 以及设置在所述第二氮化物半导体层上的绝缘图案，所述绝缘图案具有设置在所述漏电极上的上通孔，所述贯通通孔延伸到所述第一氮化物半导体层和所述第二氮化物半导体层中，并暴露出每个所述源电极的底部 。
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公开(公告)号：US10014401B2
公开(公告)日：2018-07-03
申请号：US15414156
申请日：2017-01-24
Inventor： Jeho Na , Hyung Seok Lee , Chi Hoon Jun , Sang Choon Ko , Myungjoon Kwack , Young Rak Park , Woojin Chang , Hyun-Gyu Jang , Dong Yun Jung
IPC: H01L29/778 , H01L29/20 , H01L29/205 , H01L23/31 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66
CPC classification number: H01L29/7787 , H01L23/315 , H01L23/3171 , H01L23/3178 , H01L23/3192 , H01L29/0649 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/42364 , H01L29/42372 , H01L29/66462 , H01L29/7786
Abstract: A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.
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