公开(公告)号：US20140159049A1

公开(公告)日：2014-06-12

申请号：US13905213

申请日：2013-05-30

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Choon KO ,  Jae Kyoung Mun ,  Byoung-Gue Min ,  Young Rak Park ,  Hokyun Ahn ,  Jeong-Jin Kim ,  Eun Soo Nam

IPC: H01L29/66 ,  H01L29/808

CPC classification number: H01L29/808 ,  H01L21/76898 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。

公开(公告)号：US09159583B2

公开(公告)日：2015-10-13

申请号：US14310784

申请日：2014-06-20

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Choon Ko ,  Jae Kyoung Mun ,  Woojin Chang ,  Sung-Bum Bae ,  Young Rak Park ,  Chi Hoon Jun ,  Seok-Hwan Moon ,  Woo-Young Jang ,  Jeong-Jin Kim ,  Hyungyu Jang ,  Je Ho Na ,  Eun Soo Nam

IPC: H01L21/33 ,  H01L21/321 ,  H01L21/02 ,  H01L21/283

CPC classification number: H01L21/3212 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786

Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.

Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。

公开(公告)号：US09136396B2

公开(公告)日：2015-09-15

申请号：US13905213

申请日：2013-05-30

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sang Choon Ko ,  Jae Kyoung Mun ,  Byoung-Gue Min ,  Young Rak Park ,  Hokyun Ahn ,  Jeong-Jin Kim ,  Eun Soo Nam

IPC: H01L29/66 ,  H01L29/808 ,  H01L29/417 ,  H01L29/778 ,  H01L29/43 ,  H01L29/45 ,  H01L29/20

CPC classification number: H01L29/808 ,  H01L21/76898 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.

Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。

公开(公告)号：US08952422B2

公开(公告)日：2015-02-10

申请号：US13912350

申请日：2013-06-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hokyun Ahn ,  Jong-Won Lim ,  Jeong-Jin Kim ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。

公开(公告)号：US20140167111A1

公开(公告)日：2014-06-19

申请号：US13912350

申请日：2013-06-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hokyun AHN ,  Jong-Won Lim ,  Jeong-Jin Kim ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7786

Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。