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公开(公告)号：US09780176B2
公开(公告)日：2017-10-03
申请号：US15238492
申请日：2016-08-16
Inventor： Jong Min Lee , Byoung-Gue Min , Hyung Sup Yoon , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Hae Cheon Kim , Jae Won Do , Ho Kyun Ahn , Sang-Heung Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho , Chull Won Ju
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
CPC classification number: H01L29/408 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786 , H01L29/7787
Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
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公开(公告)号：US09209266B2
公开(公告)日：2015-12-08
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won Lim , Ho Kyun Ahn , Young Rak Park , Dong Min Kang , Woo Jin Chang , Seong-il Kim , Sung Bum Bae , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/265 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/778 , H01L29/16 , H01L21/311
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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公开(公告)号：US09178474B2
公开(公告)日：2015-11-03
申请号：US13950895
申请日：2013-07-25
Inventor： Sang-Heung Lee , Seong-il Kim , Dong Min Kang , Jong-Won Lim , Chull Won Ju , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H03F3/08 , H03G1/0047 , H03G1/0088 , H03G3/02 , H03G3/3084 , H03G11/02
Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.
Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否应用固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。
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公开(公告)号：US08952422B2
公开(公告)日：2015-02-10
申请号：US13912350
申请日：2013-06-07
Inventor： Hokyun Ahn , Jong-Won Lim , Jeong-Jin Kim , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/66 , H01L29/423 , H01L29/778 , H01L29/20
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。
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公开(公告)号：US20140167111A1
公开(公告)日：2014-06-19
申请号：US13912350
申请日：2013-06-07
Inventor： Hokyun AHN , Jong-Won Lim , Jeong-Jin Kim , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/778 , H01L29/66
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。
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Patent Agency Ranking
公开(公告)号：US20140184333A1
公开(公告)日：2014-07-03
申请号：US13950895
申请日：2013-07-25
Inventor： Sang-Heung LEE , Seong-il Kim , Dong Min Kang , Jong-Won Lim , Chull Won Ju , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H03G3/30
CPC classification number: H03F3/08 , H03G1/0047 , H03G1/0088 , H03G3/02 , H03G3/3084 , H03G11/02
Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a bust packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a bust packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.
Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否施加固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。
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公开(公告)号：US20140167175A1
公开(公告)日：2014-06-19
申请号：US13914713
申请日：2013-06-11
Inventor： Seong-Il KIM , Jong-Won Lim , Dong Min Kang , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Byoung-Gue Min , Jongmin Lee , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L27/088 , H01L29/66
CPC classification number: H01L29/66477 , H01L29/1608 , H01L29/2003 , H01L29/40 , H01L29/401 , H01L29/402 , H01L29/41 , H01L29/42312 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: A field effect transistor is provided. The transistor may include a source electrode and a drain electrode provided spaced apart from each other on a substrate and a ‘+’-shaped gate electrode provided on a portion of the substrate located between the source and drain electrodes.
Abstract translation: 提供场效应晶体管。 晶体管可以包括在基板上彼此间隔开设置的源电极和漏电极，以及设置在位于源极和漏极之间的基板的一部分上的“+”形栅电极。
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公开(公告)号：US20140159050A1
公开(公告)日：2014-06-12
申请号：US13935096
申请日：2013-07-03
Inventor： Hyung Sup YOON , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Seong-ll Kim , Sang-Heung Lee , Dong Min Kang , Chull Won Ju , Jae Kyoung Mun
IPC: H01L29/778 , H01L29/66
CPC classification number: H01L29/66462 , H01L21/02118 , H01L21/0217 , H01L21/02178 , H01L21/0254 , H01L21/28264 , H01L21/28593 , H01L21/31111 , H01L21/31144 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/778 , H01L29/7786
Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.
Abstract translation: 提供场效应晶体管。 场效应晶体管可以包括衬底上的覆盖层，覆盖层上的源欧姆电极和漏极欧姆电极，堆叠在覆盖层上以覆盖源极和漏极欧姆电极的第一绝缘层和第二绝缘层， 包括脚部和头部的栅格电极，所述脚部分连接到所述源欧姆电极和所述漏极欧姆电极之间的衬底，并且所述头部从所述腿部延伸以覆盖所述源极欧姆电极和所述漏极欧姆电极的顶表面 所述第二绝缘层，在所述第二绝缘层上覆盖所述栅格电极的第一平坦化层和所述第一平坦化层上的第一电极，所述第一电极连接到所述源欧姆电极或所述漏极欧姆电极。
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公开(公告)号：US10608102B2
公开(公告)日：2020-03-31
申请号：US16137235
申请日：2018-09-20
Inventor： Hokyun Ahn , Min Jeong Shin , Jeong Jin Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Hyung Seok Lee , Jong-Won Lim , Sungjae Chang , Hyunwook Jung , Kyu Jun Cho , Dong Min Kang , Dong-Young Kim , Seong-Il Kim , Sang-Heung Lee , Jongmin Lee , Hong Gu Ji
IPC: H01L29/78 , H01L29/45 , H01L29/778 , H01L29/66 , H01L21/3065 , H01L29/417 , H01L29/06 , H01L29/20 , H01L29/423
Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.
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公开(公告)号：US10256811B2
公开(公告)日：2019-04-09
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin Chang , Jong-Won Lim , Dong Min Kang , Dong-Young Kim , Seong-il Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Min Jeong Shin , Hokyun Ahn , Hyung Sup Yoon , Sang-Heung Lee , Jongmin Lee , Sungjae Chang , Yoo Jin Jang , Hyunwook Jung , Kyu Jun Cho , Hong Gu Ji
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353 , H03K17/0812 , H03K17/10 , H03K17/12 , H03K17/14 , H03K17/16 , H03K17/28
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
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