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公开(公告)号：US09234964B2
公开(公告)日：2016-01-12
申请号：US13916250
申请日：2013-06-12
Inventor： Bongki Mheen , MyoungSook Oh , Kisoo Kim , Jae-Sik Sim , Yong-Hwan Kwon , Eun Soo Nam
CPC classification number: G01S17/89 , G01S7/4815 , G01S7/4818 , G01S7/484 , G01S7/4863
Abstract: Disclosed are a laser radar system and a method for acquiring an image of a target, and the laser radar system includes: a beam source to emit the laser beam; a beam deflector disposed between the beam source and the target, and configured to deflect the laser beam emitted from the beam source in a scanning direction of the target as time elapses; and an optical detector configured to detect the laser beam reflected from the target, which is provided a plurality of beam spots having a diameter DRBS; and a receiving optical system disposed between the target and the optical detector and configured to converge the laser beam reflected from the target, and the optical detector includes a detecting area having a diameter DDA that satisfies an equation of √{square root over (2)}×PRBS+2×DRBS≦DDA≦2×Dlens and an equation of (4/π)×λ×F_number
Abstract translation: 公开了一种用于获取目标图像的激光雷达系统和方法，并且激光雷达系统包括：发射激光束的光束源; 光束偏转器，设置在所述光束源和所述目标之间，并且被配置为随着时间的过去使从所述光束源发射的激光束沿所述目标的扫描方向偏转; 以及光检测器，被配置为检测从所述目标物反射的激光束，所述激光束设置有多个具有直径DRBS的光束点; 以及接收光学系统，其设置在所述目标和所述光学检测器之间并且被配置为会聚从所述目标物反射的所述激光束，并且所述光学检测器包括检测区域，所述检测区域具有满足方程式（2）的直径DDA， }×PRBS + 2×DRBS＆nlE; DDA＆nlE; 2×Dlens和（4 /＆pgr;）×λ×F_number
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公开(公告)号：US09209266B2
公开(公告)日：2015-12-08
申请号：US14555182
申请日：2014-11-26
Inventor： Jong-Won Lim , Ho Kyun Ahn , Young Rak Park , Dong Min Kang , Woo Jin Chang , Seong-il Kim , Sung Bum Bae , Sang-Heung Lee , Hyung Sup Yoon , Chull Won Ju , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/265 , H01L21/336 , H01L21/28 , H01L29/66 , H01L29/423 , H01L29/778 , H01L29/16 , H01L21/311
CPC classification number: H01L29/66431 , H01L21/28255 , H01L21/31116 , H01L21/31144 , H01L29/1608 , H01L29/42316 , H01L29/42376 , H01L29/66068 , H01L29/7787
Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括：在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜，所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜，所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜，所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜，第二绝缘膜和第三绝缘膜的一部分，以使源电极和漏电极露出; 以及在包括第一绝缘膜，第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。
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公开(公告)号：US09178474B2
公开(公告)日：2015-11-03
申请号：US13950895
申请日：2013-07-25
Inventor： Sang-Heung Lee , Seong-il Kim , Dong Min Kang , Jong-Won Lim , Chull Won Ju , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H03F3/08 , H03G1/0047 , H03G1/0088 , H03G3/02 , H03G3/3084 , H03G11/02
Abstract: Provided is a feedback amplifier. The feedback amplifier includes: an amplification circuit unit amplifying a burst packet signal inputted from an input terminal and outputting the amplified voltage to an output terminal; a feedback circuit unit disposed between the input terminal and the output terminal and controlling whether to apply a fixed resistance value to a signal outputted to the output terminal; a packet signal detection unit detecting a peak value of a burst packet signal from the output terminal and controlling whether to apply the fixed resistance value; and a bias circuit unit generating a bias voltage, wherein the feedback circuit unit determines a feedback resistance value to change the fixed resistance value in response to at least one control signal and adjusts a gain by receiving the bias voltage.
Abstract translation: 提供反馈放大器。 反馈放大器包括：放大电路单元，放大从输入端子输入的突发分组信号，并将放大的电压输出到输出端子; 反馈电路单元，设置在所述输入端子和所述输出端子之间，并且控制是否对输出到所述输出端子的信号施加固定电阻值; 分组信号检测单元，检测来自输出端的突发分组信号的峰值，并控制是否应用固定电阻值; 以及产生偏置电压的偏置电路单元，其中所述反馈电路单元确定反馈电阻值以响应于至少一个控制信号改变所述固定电阻值，并且通过接收所述偏置电压来调整增益。
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公开(公告)号：US09136396B2
公开(公告)日：2015-09-15
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon Ko , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808 , H01L29/417 , H01L29/778 , H01L29/43 , H01L29/45 , H01L29/20
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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公开(公告)号：US08952422B2
公开(公告)日：2015-02-10
申请号：US13912350
申请日：2013-06-07
Inventor： Hokyun Ahn , Jong-Won Lim , Jeong-Jin Kim , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/66 , H01L29/423 , H01L29/778 , H01L29/20
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。
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Patent Agency Ranking
公开(公告)号：US20140167111A1
公开(公告)日：2014-06-19
申请号：US13912350
申请日：2013-06-07
Inventor： Hokyun AHN , Jong-Won Lim , Jeong-Jin Kim , Hae Cheon Kim , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L29/778 , H01L29/66
CPC classification number: H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/51 , H01L29/518 , H01L29/66462 , H01L29/7786
Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层，以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度，并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层，以与衬底相邻。
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公开(公告)号：US20130327926A1
公开(公告)日：2013-12-12
申请号：US13915140
申请日：2013-06-11
Inventor： Yong Hwan Kwon , Bongki Mheen , Myoung Sook Oh , Jae Sik Sim , Ki Soo Kim , Eun Soo Nam
IPC: H01L27/146
CPC classification number: H01L27/146 , H01L27/14605 , H01L27/14627
Abstract: Provided is an FPA module capable of further improving a quality of an obtained 3-dimensional image by adjusting an interval of an arrangement of optical detectors and a size of the optical detector within an FPA module for obtaining the 3-dimensional image. An FPA module for obtaining a 3-dimensional image according to an exemplary embodiment of the present disclosure includes a plurality of light detectors configured to detect light reflected from a monitoring target, in which the plurality of light detectors is disposed at different intervals according to positions.
Abstract translation: 提供一种FPA模块，其能够通过调整光学检测器的布置的间隔和FPA模块内的光学检测器的尺寸来进一步提高所获得的三维图像的质量，以获得三维图像。 根据本公开的示例性实施例的用于获得三维图像的FPA模块包括多个光检测器，其被配置为检测从监视对象反射的光，其中根据位置以不同的间隔布置多个光检测器 。
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公开(公告)号：US10020201B2
公开(公告)日：2018-07-10
申请号：US15093814
申请日：2016-04-08
Inventor： Chi Hoon Jun , Sang Choon Ko , Seok-Hwan Moon , Woojin Chang , Sung-Bum Bae , Young Rak Park , Je Ho Na , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/367 , H01L21/3065 , H01L21/308 , H01L21/3205 , H01L23/473 , H01L23/467
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
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公开(公告)号：US09755027B2
公开(公告)日：2017-09-05
申请号：US15265647
申请日：2016-09-14
Inventor： Hyung Seok Lee , Ki Hwan Kim , Sang Choon Ko , Zin-Sig Kim , Jeho Na , Eun Soo Nam , Young Rak Park , Junbo Park , Chi hoon Jun , Dong Yun Jung
IPC: H01L29/66 , H01L29/40 , H01L29/778 , H01L29/423 , H01L29/20 , H01L29/417
CPC classification number: H01L29/402 , H01L29/2003 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66462 , H01L29/7786
Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
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公开(公告)号：US09159583B2
公开(公告)日：2015-10-13
申请号：US14310784
申请日：2014-06-20
Inventor： Sang Choon Ko , Jae Kyoung Mun , Woojin Chang , Sung-Bum Bae , Young Rak Park , Chi Hoon Jun , Seok-Hwan Moon , Woo-Young Jang , Jeong-Jin Kim , Hyungyu Jang , Je Ho Na , Eun Soo Nam
IPC: H01L21/33 , H01L21/321 , H01L21/02 , H01L21/283
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。
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