SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20160260653A1

    公开(公告)日:2016-09-08

    申请号:US14872868

    申请日:2015-10-01

    CPC classification number: H01L23/467

    Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate including a cantilever configured to generate a flow of cooling media through dynamic movement, an active area on the substrate which an electronic device is provided on, an insulation layer disposed to be spaced apart from the active area on the substrate, a lower electrode on the insulation layer, a piezoelectric film on the lower electrode, and an upper electrode on the piezoelectric film.

    Abstract translation: 提供一种半导体器件。 该半导体器件包括:基板,其包括悬臂,该悬臂构造成通过动态移动产生冷却介质流;基板上的有源区域,设置有电子器件;绝缘层,设置成与基板上的有源区间隔开; 绝缘层上的下电极,下电极上的压电薄膜和压电薄膜上的上电极。

    TRANSISTOR
    13.
    发明申请
    TRANSISTOR 审中-公开
    晶体管

    公开(公告)号:US20150129890A1

    公开(公告)日:2015-05-14

    申请号:US14583858

    申请日:2014-12-29

    Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.

    Abstract translation: 场效应晶体管包括依次层叠在基板上的有源层和覆盖层,以及贯穿封盖层并与活性层相邻的栅电极。 栅电极包括与有源层相邻的脚部和具有大于脚部的宽度的宽度的头部。 栅电极的端部的脚部的宽度小于栅电极的另一部分的头部的宽度,并且大于栅极的另一部分的脚部的宽度。 栅电极的端部的脚部进一步穿过有源层,以与衬底相邻。

    APPARATUS FOR OBTAINING 3D INFORMATION USING PHOTODETECTOR ARRAY
    15.
    发明申请
    APPARATUS FOR OBTAINING 3D INFORMATION USING PHOTODETECTOR ARRAY 审中-公开
    使用光电转换阵列获取3D信息的设备

    公开(公告)号:US20130341486A1

    公开(公告)日:2013-12-26

    申请号:US13755470

    申请日:2013-01-31

    Abstract: The present disclosure relates to an apparatus for obtaining 3D information using a photodetector array. The apparatus for obtaining 3D information includes: a light source unit configured to generate an optical signal of a predetermined wavelength band; a light transmission optical lens unit provided on a path of the optical signal and configured to emit the optical signal output from the light source unit in parallel or at a predetermined angle; an optical scanning unit configured to scan the light output from the light transmission optical lens unit to a surface of an object to be measured; a light reception optical lens unit configured to collect the light reflected from the surface of the object; and a photodetection unit configured to convert collected optical signals into respective electrical signals by arraying one or more photodetectors such that light reception portions thereof are collected at a center.

    Abstract translation: 本公开涉及一种使用光电检测器阵列获得3D信息的装置。 用于获得3D信息的装置包括:光源单元,被配置为产生预定波长带的光信号; 光传输光学透镜单元,设置在所述光信号的路径上并被配置为平行地或以预定角度发射从所述光源单元输出的光信号; 光扫描单元,被配置为将从所述光传输光学透镜单元输出的光扫描到待测量对象的表面; 光接收光学透镜单元,被配置为收集从所述物体的表面反射的光; 以及光检测单元,被配置为通过排列一个或多个光电检测器将收集的光信号转换成各个电信号,使得其中的光接收部分被收集。

    HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF
    18.
    发明申请
    HIGH ELECTRON MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
    高电子移动晶体管及其制造方法

    公开(公告)号:US20150087142A1

    公开(公告)日:2015-03-26

    申请号:US14555182

    申请日:2014-11-26

    Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.

    Abstract translation: 公开了一种高电子迁移率晶体管的制造方法。 该方法包括:在基板上形成源电极和漏电极; 在所述基板的整个表面上形成具有第一开口的第一绝缘膜,所述第一开口暴露所述基板的一部分; 在所述第一开口内形成具有第二开口的第二绝缘膜,所述第二开口暴露所述基板的一部分; 在所述第二开口内形成具有第三开口的第三绝缘膜,所述第三开口暴露所述基板的一部分; 蚀刻第一绝缘膜,第二绝缘膜和第三绝缘膜的一部分,以使源电极和漏电极露出; 以及在包括第一绝缘膜,第二绝缘膜和第三绝缘膜的支撑结构上形成T栅电极。

    AlGaN TEMPLATE FABRICATION METHOD AND STRUCTURE OF THE AlGaN TEMPLATE
    19.
    发明申请
    AlGaN TEMPLATE FABRICATION METHOD AND STRUCTURE OF THE AlGaN TEMPLATE 审中-公开
    AlGaN模板制备方法和AlGaN模板的结构

    公开(公告)号:US20140225121A1

    公开(公告)日:2014-08-14

    申请号:US14143716

    申请日:2013-12-30

    Abstract: Provided are an aluminum gallium nitride template and a fabrication method thereof. The fabrication method includes forming an aluminum nitride (AlN) layer on a substrate, forming a first aluminum gallium nitride (AlxGa1-xN) layer on the aluminum nitride (AlN) layer, forming a second aluminum gallium nitride (AlyGa1-yN) layer on the first aluminum gallium nitride (AlxGa1-xN) layer, forming a third aluminum gallium nitride (AlzGa1-zN) layer on the second aluminum gallium nitride (AlyGal-yN) layer, wherein the first aluminum gallium nitride (AlxGa1-xN) layer, the second aluminum gallium nitride (AlyGa1-yN) layer, and the third aluminum gallium nitride (AlzGa1-zN) layer are formed to have crystal defects and a composition ratio of aluminum (where 1>x>y>z>0) that are gradually decreased as heights of the layers are increased.

    Abstract translation: 提供了一种氮化镓铝模板及其制造方法。 制造方法包括在基板上形成氮化铝(AlN)层,在氮化铝(AlN)层上形成第一氮化镓铝(Al x Ga 1-x N)层,在第一铝氮化镓(AlAlGa1-xN)层上形成第二氮化镓铝 所述第一氮化镓铝(Al x Ga 1-x N)层,在所述第二氮化铝镓(AlyGal-yN)层上形成第三氮化镓铝(AlzGa1-zN)层,其中所述第一氮化镓铝(Al x Ga 1-x N) 第二氮化镓铝(Al y Ga 1-y N)层和第三氮化镓铝(AlzGa1-zN)层形成为具有晶体缺陷和铝(其中1> x> y> z> 0)的组成比为 随着层数的增加而逐渐减小。

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