Abstract:
A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
Abstract:
Provided is a semiconductor device. The semiconductor device includes a substrate including a cantilever configured to generate a flow of cooling media through dynamic movement, an active area on the substrate which an electronic device is provided on, an insulation layer disposed to be spaced apart from the active area on the substrate, a lower electrode on the insulation layer, a piezoelectric film on the lower electrode, and an upper electrode on the piezoelectric film.
Abstract:
A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
Abstract:
Provided is a method of measuring signal transmission time difference of a measuring device. The measuring device according to embodiments, by measuring a skew on two optical paths through signal delays of sufficient sizes for skew measurement on the optical paths, even a skew having a minute size can be measured within a measureable range.
Abstract:
The present disclosure relates to an apparatus for obtaining 3D information using a photodetector array. The apparatus for obtaining 3D information includes: a light source unit configured to generate an optical signal of a predetermined wavelength band; a light transmission optical lens unit provided on a path of the optical signal and configured to emit the optical signal output from the light source unit in parallel or at a predetermined angle; an optical scanning unit configured to scan the light output from the light transmission optical lens unit to a surface of an object to be measured; a light reception optical lens unit configured to collect the light reflected from the surface of the object; and a photodetection unit configured to convert collected optical signals into respective electrical signals by arraying one or more photodetectors such that light reception portions thereof are collected at a center.
Abstract:
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
Abstract:
Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
Abstract:
Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
Abstract:
Provided are an aluminum gallium nitride template and a fabrication method thereof. The fabrication method includes forming an aluminum nitride (AlN) layer on a substrate, forming a first aluminum gallium nitride (AlxGa1-xN) layer on the aluminum nitride (AlN) layer, forming a second aluminum gallium nitride (AlyGa1-yN) layer on the first aluminum gallium nitride (AlxGa1-xN) layer, forming a third aluminum gallium nitride (AlzGa1-zN) layer on the second aluminum gallium nitride (AlyGal-yN) layer, wherein the first aluminum gallium nitride (AlxGa1-xN) layer, the second aluminum gallium nitride (AlyGa1-yN) layer, and the third aluminum gallium nitride (AlzGa1-zN) layer are formed to have crystal defects and a composition ratio of aluminum (where 1>x>y>z>0) that are gradually decreased as heights of the layers are increased.
Abstract translation:提供了一种氮化镓铝模板及其制造方法。 制造方法包括在基板上形成氮化铝(AlN)层,在氮化铝(AlN)层上形成第一氮化镓铝(Al x Ga 1-x N)层,在第一铝氮化镓(AlAlGa1-xN)层上形成第二氮化镓铝 所述第一氮化镓铝(Al x Ga 1-x N)层,在所述第二氮化铝镓(AlyGal-yN)层上形成第三氮化镓铝(AlzGa1-zN)层,其中所述第一氮化镓铝(Al x Ga 1-x N) 第二氮化镓铝(Al y Ga 1-y N)层和第三氮化镓铝(AlzGa1-zN)层形成为具有晶体缺陷和铝(其中1> x> y> z> 0)的组成比为 随着层数的增加而逐渐减小。
Abstract:
The present disclosure relates to a nitride electronic device and a method for manufacturing the same, and particularly, to a nitride electronic device and a method for manufacturing the same that can implement various types of nitride integrated structures on the same substrate through a regrowth technology (epitaxially lateral over-growth: ELOG) of a semi-insulating gallium nitride (GaN) layer used in a III-nitride semiconductor electronic device including Group III elements such as gallium (Ga), aluminum (Al) and indium (In) and nitrogen.