公开(公告)号：US20230343644A1

公开(公告)日：2023-10-26

申请号：US18070383

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Chih-Hsun HSU ,  Shiyu YUE ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG ,  Zhenjiang CUI ,  Chi Hong CHING ,  Meng-Shan WU ,  Chun-chieh WANG ,  Wei LEI ,  Yu LEI

IPC: H01L21/768 ,  H01L21/67 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/67063 ,  H01L21/6719 ,  H01L21/76843 ,  H01L21/76871 ,  H01L23/53266

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20230343643A1

公开(公告)日：2023-10-26

申请号：US17868475

申请日：2022-07-19

Applicant: Applied Materials, Inc.

Inventor： Chih-Hsun HSU ,  Shiyu YUE ,  Wei LEI ,  Yi XU ,  Jiang LU ,  Yu LEI ,  Ziye XIONG ,  Tsung-Han YANG ,  Zhimin QI ,  Aixi ZHANG ,  Jie ZHANG ,  Liqi WU ,  Rongjun WANG ,  Shihchung CHEN ,  Meng-Shan WU ,  Chun-Chieh WANG ,  Annamalai LAKSHMANAN ,  Yixiong YANG ,  Xianmin TANG

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76877 ,  H01L21/76876 ,  H01L21/76843 ,  H01L21/76865 ,  H01L23/5226 ,  H01L21/76826

Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

公开(公告)号：US20190305217A1

公开(公告)日：2019-10-03

申请号：US16276128

申请日：2019-02-14

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Xiaodong WANG ,  Mahendra PAKALA ,  Rongjun WANG

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22

Abstract: Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced.

公开(公告)号：US20180010242A1

公开(公告)日：2018-01-11

申请号：US15632921

申请日：2017-06-26

Applicant: Applied Materials, Inc.

Inventor： Muhammad RASHEED ,  Keith A. MILLER ,  Rongjun WANG

IPC: C23C14/50 ,  C23C16/458 ,  C23C14/56 ,  H01L21/687 ,  C23C14/34

CPC classification number: C23C14/50 ,  C23C14/3407 ,  C23C14/564 ,  C23C16/4585 ,  H01L21/68735

Abstract: Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a deposition ring and a pedestal assembly. The components of the process kit work alone, and in combination, to significantly reduce their effects on the electric fields around a substrate during processing.

公开(公告)号：US20170125215A1

公开(公告)日：2017-05-04

申请号：US14986168

申请日：2015-12-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Yana CHENG ,  Zhefeng LI ,  Chi Hong CHING ,  Yong CAO ,  Rongjun WANG

IPC: H01J37/32 ,  C23C14/34

Abstract: Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

公开(公告)号：US20150114827A1

公开(公告)日：2015-04-30

申请号：US14062610

申请日：2013-10-24

Applicant: Applied Materials, Inc.

Inventor： Yong CAO ,  Tingjun XU ,  Rajkumar JAKKARAJU ,  Rongjun WANG

IPC: H01L21/02 ,  C23C14/34

CPC classification number: H01L21/02266 ,  C23C14/0036 ,  C23C14/0676 ,  H01L21/02178 ,  H01L21/31111

Abstract: Methods for forming a metal dielectric etching stop layer onto a substrate with good etching selectivity and low wet etching rate. In one embodiment, a method of sputter depositing a metal dielectric etching stop layer on the substrate includes transferring a substrate in a processing chamber, supplying a gas mixture including at least N2 gas into the processing chamber, applying a RF power to form a plasma from the gas mixture to sputter source material from a target disposed in the processing chamber, maintaining a substrate temperature less than about 320 degrees Celsius, and depositing a metal dielectric etching stop layer onto the substrate from the sputtered source material.

Abstract translation: 在具有良好蚀刻选择性和低湿蚀刻速率的基板上形成金属电介质蚀刻停止层的方法。 在一个实施例中，在衬底上溅射沉积金属电介质蚀刻停止层的方法包括在处理室中转移衬底，将至少包括N 2气体的气体混合物供应到处理室中，施加RF功率以形成等离子体 所述气体混合物从设置在所述处理室中的靶溅射源材料，保持低于约320摄氏度的衬底温度，以及从所述溅射源材料在所述衬底上沉积金属电介质蚀刻停止层。

公开(公告)号：US20250157824A1

公开(公告)日：2025-05-15

申请号：US18947949

申请日：2024-11-14

Applicant: Applied Materials, Inc.

Inventor： Shumao ZHANG ,  Qihao ZHU ,  Liqi WU ,  Chih-Hsun HSU ,  Jiang LU ,  Rongjun WANG

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/458 ,  C23C16/52 ,  H01L21/02

Abstract: Embodiments of the present disclosure generally relate to methods and processes for selectively depositing a metal fill layer into a feature on the surface of a semiconductor structure. In some embodiments, a method of forming a contact structure includes performing a preclean operation on a contact structure to form a precleaned contact structure. The contact structure includes a silicon-based portion exposed in a cavity of a substrate. The method further includes depositing a metal layer over the precleaned contact structure to form a deposited contact structure. The method further includes introducing a metal halide precursor to the deposited contact structure to at least partially remove the second layer from the deposited contact structure to form an etched contact structure. The method further includes depositing a metal fill layer onto the first layer to form a filled contact structure. The deposited metal fill layer comprises a super conformal profile.

公开(公告)号：US20240371654A1

公开(公告)日：2024-11-07

申请号：US18142940

申请日：2023-05-03

Applicant: Applied Materials, Inc.

Inventor： Qihao ZHU ,  Chi Hong CHING ,  Liqi WU ,  Tsungjui LIU ,  Gaurav THAREJA ,  Xinke WANG ,  Feng Q. LIU ,  Xi CEN ,  Kai WU ,  Yixiong YANG ,  Yuanhung LIU ,  Jiang LU ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/768

Abstract: A method of filling a feature in a semiconductor structure with metal includes depositing a metal cap layer on a bottom surface of a feature formed within a dielectric layer and top surfaces of the dielectric layer, partially filling the feature from the bottom surface with a flowable polymer layer, performing a metal pullback process to remove the metal cap layer on the top surfaces of the dielectric layer selectively to the dielectric layer, wherein the metal pullback process includes a first etch process including a chemical etch process using molybdenum hexafluoride (MoF6) to remove the metal cap layer selectively to the dielectric layer, and a second etch process to remove residues on etched surfaces of the dielectric layer, removing the flowable polymer layer, pre-cleaning a surface of the metal cap layer, and filling the feature from the surface of the metal cap layer with metal fill material.

公开(公告)号：US20240355673A1

公开(公告)日：2024-10-24

申请号：US18136970

申请日：2023-04-20

Applicant: Applied Materials, Inc.

Inventor： Wei LEI ,  Sahil PATEL ,  Yixiong YANG ,  Yu LEI ,  Shiyu YUE ,  Yi XU ,  Tuerxun AILIHUMAER ,  Juhyun OH ,  Xianmin TANG ,  Rongjun WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  C23C14/18 ,  H01L21/02063 ,  H01L21/28568

Abstract: Semiconductor devices and methods for molybdenum fill in semiconductor devices are provided. In one aspect, a method for processing a semiconductor device substrate is provided. The method includes exposing at least one feature formed in a dielectric layer to a grain modification layer deposition process to deposit a grain modification layer over at least a portion of the at least one feature. The at least one feature is defined by sidewall surfaces formed in the dielectric layer and a bottom surface extending between the sidewall surfaces. The method further includes exposing the at least one feature to a molybdenum deposition process to form a molybdenum-fill layer on the grain modification layer, wherein the grain modification layer comprises a metal different from molybdenum.

公开(公告)号：US20240105444A1

公开(公告)日：2024-03-28

申请号：US18139590

申请日：2023-04-26

Applicant: Applied Materials, Inc.

Inventor： Jiang LU ,  Liqi WU ,  Wei DOU ,  Weifeng YE ,  Shih Chung CHEN ,  Rongjun WANG ,  Xianmin TANG ,  Yiyang WAN ,  Shumao ZHANG ,  Jianqiu GUO

IPC: H01L21/02 ,  C23C16/04

CPC classification number: H01L21/0217 ,  C23C16/045 ,  H01L21/02274 ,  H01L21/0228

Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.