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公开(公告)号:US20170291199A1
公开(公告)日:2017-10-12
申请号:US15485105
申请日:2017-04-11
Applicant: Applied Materials, Inc.
Inventor: Xing ZHONG , Zhijun CHEN , Zhenjiang CUI , Nitin K. INGLE
CPC classification number: H01L21/02057 , H01L21/76224
Abstract: A method for removing halogen from a surface of a substrate is described herein. The method described herein includes flowing oxygen gas and an inert gas such as nitrogen gas into a RPS. The gases in the RPS are energized to form oxygen radicals and nitrogen radicals. The oxygen and nitrogen radicals are used to remove halogen content on the surface of the substrate. The chamber pressure of the halogen content removal process is very low, ranging from about 50 mTorr to about 100 mTorr. By using oxygen gas and an inert gas and with a low chamber pressure, the halogen content on the surface of the substrate is reduced while keeping the oxidation level of the surface of the substrate to at most 10 Angstroms.
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公开(公告)号:US20180182777A1
公开(公告)日:2018-06-28
申请号:US15855465
申请日:2017-12-27
Applicant: Applied Materials, Inc.
Inventor: Zhenjiang CUI , Hanshen ZHANG , Anchuan WANG , Zhijun CHEN , Nitin K. INGLE
IPC: H01L27/11582 , H01L21/311 , H01L21/3213 , H01L23/31 , H01L23/29 , H01L27/11556 , H01L21/67
Abstract: Embodiments of the present disclosure provide methods for forming features in a film stack. The film stack may be utilized to form stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes exposing a substrate having a multi-material layer formed thereon to radicals of a remote plasma to form one or more features through the multi-material layer, the one or more features exposing a portion of a top surface of the substrate, and the multi-material layer comprising alternating layers of a first layer and a second layer, wherein the remote plasma is formed from an etching gas mixture comprising a fluorine-containing chemistry, and wherein the process chamber is maintained at a pressure of about 2 Torr to about 20 Torr and a temperature of about −100° C. to about 100° C.
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公开(公告)号:US20170338119A1
公开(公告)日:2017-11-23
申请号:US15161783
申请日:2016-05-23
Applicant: Applied Materials, Inc.
Inventor: Hanshen ZHANG , Jie LIU , Zhenjiang CUI
IPC: H01L21/3065
CPC classification number: H01L21/3065 , H01J37/32357 , H01J37/32422 , H01L21/31122
Abstract: In one implementation, a method of removing a metal-containing layer is provided. The method comprises generating a plasma from a fluorine-containing gas. The plasma comprises fluorine radicals and fluorine ions. The fluorine ions are removed from the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions. A substrate comprising a metal-containing layer is exposed to the reactive gas. The reactive gas dopes at least a portion of the metal-containing layer to form a metal-containing layer doped with fluorine radicals. The metal-containing layer doped with fluorine radicals is exposed to a nitrogen and hydrogen containing gas mixture and the reactive gas to remove at least a portion of the metal-containing layer doped with fluorine radicals.
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公开(公告)号:US20150170956A1
公开(公告)日:2015-06-18
申请号:US14523523
申请日:2014-10-24
Applicant: Applied Materials, Inc.
Inventor: Mehul B. NAIK , He REN , Zhenjiang CUI
IPC: H01L21/768 , H01L21/311 , H01L21/02
CPC classification number: H01L21/7682 , C23C16/303 , C23C16/36 , H01J37/32082 , H01L21/02167 , H01L21/0217 , H01L21/31116 , H01L21/31138 , H01L21/76819 , H01L21/76832 , H01L21/76834
Abstract: A method for forming an air gap structure in an integrated layer stack includes dry etching a mold layer disposed on the stack in a processing system under vacuum. The mold layer is disposed between one or more interconnects, and the process of dry etching of the mold layer exposes at least a portion of the interconnects. The method also includes depositing a liner layer over the exposed portion of the interconnects. In another embodiment, a method for forming an air gap structure in an integrated layer stack includes dry etching an oxide mold layer disposed on the stack in an a first processing chamber in a processing system under vacuum. The method also includes depositing a low-k material liner layer over the interconnects, wherein the liner has a thickness of less than about 2 nanometers. The methods disclosed herein are performed in a processing system without breaking vacuum.
Abstract translation: 在一体层叠体中形成气隙结构的方法包括在真空下在处理系统中干燥蚀刻设置在堆叠上的模具层。 模具层设置在一个或多个互连之间,并且模具层的干蚀刻的过程暴露至少一部分互连。 该方法还包括在互连的暴露部分上沉积衬垫层。 在另一实施例中,在一体层叠体中形成气隙结构的方法包括在真空下在处理系统中的第一处理室中干燥蚀刻设置在堆叠上的氧化物模层。 所述方法还包括在所述互连件上沉积低k材料衬垫层,其中所述衬垫具有小于约2纳米的厚度。 本文公开的方法在不破坏真空的处理系统中进行。
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公开(公告)号:US20230343644A1
公开(公告)日:2023-10-26
申请号:US18070383
申请日:2022-11-28
Applicant: Applied Materials, Inc.
Inventor: Chih-Hsun HSU , Shiyu YUE , Jiang LU , Rongjun WANG , Xianmin TANG , Zhenjiang CUI , Chi Hong CHING , Meng-Shan WU , Chun-chieh WANG , Wei LEI , Yu LEI
IPC: H01L21/768 , H01L21/67 , H01L23/532
CPC classification number: H01L21/76877 , H01L21/67063 , H01L21/6719 , H01L21/76843 , H01L21/76871 , H01L23/53266
Abstract: A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.
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公开(公告)号:US20170294320A1
公开(公告)日:2017-10-12
申请号:US15484527
申请日:2017-04-11
Applicant: Applied Materials, Inc.
Inventor: Zhenjiang CUI , Xing ZHONG , Jie LIU , Linlin WANG
IPC: H01L21/3213 , H01L29/51 , H01L21/28 , H01L29/49 , H01L29/66
CPC classification number: H01L21/32136 , H01J37/32357 , H01J37/32422 , H01L21/02071 , H01L21/28088 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L29/4966 , H01L29/517 , H01L29/66795
Abstract: A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.
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7.
公开(公告)号:US20160049331A1
公开(公告)日:2016-02-18
申请号:US14923957
申请日:2015-10-27
Applicant: Applied Materials, Inc.
Inventor: Mehul B. NAIK , Abhijit Basu MALLICK , Kiran V. THADANI , Zhenjiang CUI
IPC: H01L21/768
CPC classification number: H01L21/76885 , H01L21/76834 , H01L21/76852 , H01L21/76867 , H01L23/53233 , H01L23/53238 , H01L23/53261 , H01L23/53266 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.
Abstract translation: 本发明的实施例一般涉及用于形成金属结构和钝化层的方法。 在一个实施例中,在衬底上形成金属柱。 金属柱掺杂有锰,铝,锆或铪。 介电材料沉积在金属柱之上和之间,然后固化以在金属柱的垂直表面上形成钝化层。
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