公开(公告)号：US20160319428A1

公开(公告)日：2016-11-03

申请号：US14750322

申请日：2015-06-25

Applicant: APPLIED MATERIALS, INC.

Inventor： Muhammad M. RASHEED ,  Balasubramanian RAMACHANDRAN ,  Shih Chung CHEN ,  Kevin A. PAPKE ,  Lei ZHOU ,  Jing ZHOU

IPC: C23C16/455 ,  C23C16/458

CPC classification number: C23C16/45544 ,  C23C16/4404 ,  C23C16/45565

Abstract: Methods and apparatus for processing a substrate are provided herein. In some embodiments, a process chamber includes: a chamber body and a lid assembly defining a processing volume within the process chamber; a substrate support disposed within the processing volume to support a substrate; and a showerhead having a first surface including a plurality of gas distribution holes disposed opposite and parallel to the substrate support, wherein the showerhead is fabricated from aluminum and includes an aluminum oxide coating along the first surface, wherein the aluminum oxide coating has a thickness of about 0.0001 to about 0.002 inches. In some embodiments, the showerhead may further have at least one of a roughness of about 10 to about 300μ-in Ra, or an emissivity (ε) of about 0.20 to about 0.80. The process chamber may be a thermal atomic layer deposition (ALD) chamber.

Abstract translation: 本文提供了用于处理衬底的方法和设备。 在一些实施例中，处理室包括：室主体和限定处理室内的处理容积的盖组件; 设置在所述处理体积内以支撑衬底的衬底支撑件; 以及具有第一表面的喷头，所述第一表面包括与所述基板支撑件相对并平行设置的多个气体分配孔，其中所述喷头由铝制成并且包括沿着所述第一表面的氧化铝涂层，其中所述氧化铝涂层的厚度为 约0.0001至约0.002英寸。 在一些实施例中，喷头还可以具有在Ra中约10至约300μ的粗糙度或约0.20至约0.80的发射率（ε）中的至少一种。 处理室可以是热原子层沉积（ALD）室。

公开(公告)号：US20240105444A1

公开(公告)日：2024-03-28

申请号：US18139590

申请日：2023-04-26

Applicant: Applied Materials, Inc.

Inventor： Jiang LU ,  Liqi WU ,  Wei DOU ,  Weifeng YE ,  Shih Chung CHEN ,  Rongjun WANG ,  Xianmin TANG ,  Yiyang WAN ,  Shumao ZHANG ,  Jianqiu GUO

IPC: H01L21/02 ,  C23C16/04

CPC classification number: H01L21/0217 ,  C23C16/045 ,  H01L21/02274 ,  H01L21/0228

Abstract: Methods for reducing contact resistance include performing a selective titanium silicide (TiSi) deposition process on a middle of the line (MOL) contact structure that includes a cavity in a substrate of dielectric material. The contact structure also includes a silicon-based connection portion at a bottom of the cavity. The selective TiSi deposition process is selective to silicon-based material over dielectric material. The methods also include performing a selective deposition process of a metal material on the MOL contact structure. The selective deposition process is selective to TiSi material over dielectric material and forms a silicide capping layer on the silicon-based connection portion. The methods further include performing a seed layer deposition process of the metal material on the contact structure.

公开(公告)号：US20170179252A1

公开(公告)日：2017-06-22

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. TANG ,  Paul F. MA ,  Steven C. H. HUNG ,  Michael CHUDZIK ,  Siddarth KRISHNAN ,  Wenyu ZHANG ,  Seshadri GANGULI ,  Naomi YOSHIDA ,  Lin DONG ,  Yixiong YANG ,  Liqi WU ,  Shih Chung CHEN

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.