公开(公告)号：US20240234321A1

公开(公告)日：2024-07-11

申请号：US18429873

申请日：2024-02-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hiranmay BISWAS ,  Chi-Yeh YU ,  Kuo-Nan YANG ,  Chung-Hsing WANG ,  Stefan RUSU ,  Chin-Shen LIN

IPC分类号： H01L23/528 ,  G06F30/394 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  G06F30/394

摘要： A conductive line structure includes: first and second offset sets of long pillars that are substantially coaxial on an intra-set basis; a third set of offset short pillars, the short pillars being: overlapping of long pillars in the first and second sets; and organized into groups of first quantities of the short pillars; each of the groups being overlapping of and electrically coupled between a pair of one of the long pillars in the first set and a one of the long pillars in the second set such that, in each of the groups, each short pillar being overlapping of and electrically coupled between the pair; and each long pillar in each of the first and second sets being overlapped by a second quantity of short pillars in the third set and being electrically coupled to same; and the first quantity being less than the second quantity.

公开(公告)号：US12034086B1

公开(公告)日：2024-07-09

申请号：US17552269

申请日：2021-12-15

申请人： Kepler Computing Inc.

发明人： Somilkumar J. Rathi ,  Noriyuki Sato ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Tanay Gosavi ,  Pratyush Pandey ,  Jason Y. Wu ,  Sasikanth Manipatruni

IPC分类号： H10B53/30 ,  H01L21/768 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02

CPC分类号： H01L29/945 ,  H01L21/76834 ,  H01L21/7687 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L28/57 ,  H01L28/65 ,  H01L28/75 ,  H10B53/30

摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

公开(公告)号：US12033939B2

公开(公告)日：2024-07-09

申请号：US16696929

申请日：2019-11-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shien-Yang Wu ,  Wei-Chang Kung

IPC分类号： H01L23/525 ,  H01L23/522

CPC分类号： H01L23/5256 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an anode, a cathode, and a fuse link extending between the anode and the cathode. A plurality of anode contacts are coupled to the anode, and a plurality of cathode contacts are coupled to the cathode. The plurality of cathode contacts are arranged symmetrically with respect to a centerline of the fuse link.

公开(公告)号：US12033889B2

公开(公告)日：2024-07-09

申请号：US18097418

申请日：2023-01-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

摘要： An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

公开(公告)号：US20240224533A1

公开(公告)日：2024-07-04

申请号：US18605115

申请日：2024-03-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Changsun Hwang ,  Youngjin Kwon ,  Gihwan Kim ,  Hansol Seok ,  Dongseog Eun ,  Jongheun Lim

IPC分类号： H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC分类号： H10B43/40 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

摘要： An integrated circuit device includes: a substrate having a cell region, a peripheral circuit region, and an interconnection region between the cell region and the peripheral circuit region; a first cell stack structure and a second cell stack structure on the first cell stack structure, each including a plurality of insulating layers and a plurality of word line structures alternately stacked on the substrate; and a dummy stack structure located at a same vertical level as the second cell stack structure, and including a plurality of dummy insulating layers and a plurality of dummy support layers alternately stacked in the peripheral circuit region.

公开(公告)号：US20240222508A1

公开(公告)日：2024-07-04

申请号：US18438758

申请日：2024-02-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shi Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC分类号： H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/6681 ,  H01L21/76224 ,  H01L21/823418

摘要： A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.

公开(公告)号：US20240222274A1

公开(公告)日：2024-07-04

申请号：US18147820

申请日：2022-12-29

申请人： Intel Corporation

发明人： Praneeth Kumar Akkinepally ,  Sivakumar Nagarajan ,  Nisha Ananthakrishnan ,  Santosh Shaw ,  Wei Gao

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L23/5283 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06541

摘要： Integrated circuit (IC) dies, microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, an IC die may include a substrate, a front-end-of-line (FEOL) layer over the substrate, where the FEOL layer includes a plurality of transistors, a first back-end-of-line (BEOL) layer comprising first interconnects, a second BEOL layer comprising second interconnects, and a third BEOL layer comprising third interconnects, wherein the first BEOL layer is between the FEOL layer and the second BEOL layer, the second BEOL layer is between the first BEOL layer and the third BEOL layer, and an electrically conductive fill material of the second interconnects is different from an electrically conductive fill material of the first interconnects and from an electrically conductive fill material of the third interconnects.

公开(公告)号：US20240222272A1

公开(公告)日：2024-07-04

申请号：US18090838

申请日：2022-12-29

申请人： Intel Corporation

发明人： Abhishek Anil SHARMA ,  Christopher M. PELTO ,  Wilfred GOMES ,  Tahir GHANI ,  Anand S. MURTHY

IPC分类号： H01L23/528 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L25/105

摘要： Stitched dies having double interconnects are described. For example, an integrated circuit structure includes a first die including a first device layer, a first plurality of metallization layers over the first device layer, and a first conductive interconnection over the first plurality of metallization layers. The integrated circuit structure also includes a second die separated from the first die by a scribe region, the second die including a second device layer, a second plurality of metallization layers over the second device layer, and a second conductive interconnection over the second plurality of metallization layers. The second conductive interconnection extends over the scribe region and is coupled to the first conductive interconnection.

公开(公告)号：US20240222267A1

公开(公告)日：2024-07-04

申请号：US18396813

申请日：2023-12-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Byoungil LEE ,  Seungbeom KO ,  Jongyoon CHOI

IPC分类号： H01L23/522 ,  G11C16/04 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC分类号： H01L23/5226 ,  G11C16/0483 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

摘要： A semiconductor device comprising: a stack structure on a substrate including gate electrodes and insulating layers alternately stacked; a first through via extending through the stack structure; and a second through via spaced apart from the first through via, wherein the second through via extends through the stack structure, wherein the second through via is electrically connected to a first gate electrode that is farthest one among the gate electrodes from the substrate in the vertical direction, wherein a gate pad is on and contacts the first gate electrode, and the first through via includes: a vertical pattern; first and second protrusions that protrude from the vertical pattern, wherein the first protrusion overlaps a portion of the first gate electrode in the horizontal direction; and the second protrusion overlaps a second gate electrode in the horizontal direction, wherein the second gate electrode is spaced apart from the second through via.

公开(公告)号：US20240222265A1

公开(公告)日：2024-07-04

申请号：US18239156

申请日：2023-08-29

申请人： Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

发明人： Xinghua WANG ,  Qiankun XU

IPC分类号： H01L23/522 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L23/5225 ,  H01L23/5226 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/7869

摘要： A thin film transistor array substrate includes a base substrate, a light shielding layer, a semiconductor layer, a gate insulating layer, a gate layer, and a source-drain metal layer in contact with the semiconductor layer and in contact with the light shielding layer sequentially disposed on the base substrate, a first insulating layer covering the source-drain metal layer disposed on the base substrate, and a metal protection layer disposed on the first insulating layer. The semiconductor layer, the gate layer, and the source-drain metal layer form a thin film transistor. An end of the metal protection layer is in contact with the source-drain metal layer, and another end of the metal protection layer is in contact with the light shielding layer.