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公开(公告)号：US20230361105A1
公开(公告)日：2023-11-09
申请号：US18355273
申请日：2023-07-19
发明人： Wei-Ren CHEN , Cheng-Yu LIN , Hui-Zhong ZHUANG , Yung-Chen CHIEN , Jerry Chang Jui KAO , Huang-Yu CHEN , Chung-Hsing WANG
IPC分类号： H01L27/02 , H01L27/092 , G06F30/394 , H01L21/8238 , G06F30/392 , H01L23/522
CPC分类号： H01L27/0207 , H01L27/092 , G06F30/394 , H01L21/823871 , G06F30/392 , H01L23/5226
摘要： An integrated circuit (IC) device includes a substrate, at least one active region over the substrate and elongated along a first axis, at least one gate region extending across the at least one active region, and at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to other circuitry. The at least one IO pattern extends obliquely to the at least one active region or the at least one gate region.
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公开(公告)号：US20230343703A1
公开(公告)日：2023-10-26
申请号：US17727504
申请日：2022-04-22
发明人： Chih-Yu LAI , Chih-Liang CHEN , Chi-Yu LU , Chung-Hsing WANG
IPC分类号： H01L23/528 , H01L23/48 , H01L23/522 , H01L21/768
CPC分类号： H01L23/528 , H01L23/481 , H01L23/5226 , H01L21/76898
摘要： A semiconductor device includes a substrate. The semiconductor device further includes a conductive mesh on a first side of the substrate. The semiconductor device further includes an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate. The semiconductor device further includes a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate. The semiconductor device further includes a contact structure on the second side of the substrate, wherein the contact structure is electrically connected to the active region, the contact structure is in direct contact with the through via, and the contact structure overlaps a top surface of the through via in a top view.
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公开(公告)号：US20220245318A1
公开(公告)日：2022-08-04
申请号：US17353991
申请日：2021-06-22
发明人： Yen-Pin CHEN , Florentin DARTU , Wei-Chih HSIEH , Tzu-Hen LIN , Chung-Hsing WANG
IPC分类号： G06F30/392 , G06F30/398 , G06F30/327
摘要： For a method of manufacturing a semiconductor device, a corresponding layout diagram is stored on a non-transitory computer-readable medium, the layout diagram being arranged relative to first and second perpendicular directions, the layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction. The method includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information. For each cell in the subset of the cells, the generating a sidefile includes populating the sidefile with a first neighbor-specific proximity-effect (NSPE) parameter corresponding to an inter-cell proximity-effect induced by the first neighbor cell and a second NSPE parameter corresponding to an inter-cell proximity-effect induced by the second neighbor cell.
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公开(公告)号：US20220093513A1
公开(公告)日：2022-03-24
申请号：US17544937
申请日：2021-12-08
发明人： Hiranmay BISWAS , Chi-Yeh YU , Kuo-Nan YANG , Chung-Hsing WANG , Stefan RUSU , Chin-Shen LIN
IPC分类号： H01L23/528 , H01L21/768 , H01L23/522
摘要： A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.
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公开(公告)号：US20200074042A1
公开(公告)日：2020-03-05
申请号：US16547065
申请日：2019-08-21
发明人： Hiranmay BISWAS , Chung-Hsing WANG , Kuo-Nan YANG , Jia Han LIN
摘要： A method (of manufacturing a semiconductor device) includes, for a layout diagram stored on a non-transitory computer-readable medium, generating the layout diagram including: populating a row which extends in a first direction with a group of cells, each cell representing a circuit, and first and second side boundaries of each cell being substantially parallel and extending in a second direction which is substantially perpendicular to the first direction; locating, relative to the first direction, cells so that neighboring ones of the cells are substantially abutting; and reducing an aggregate leakage tendency of the group by performing at least one of the following, (A) changing an orientation of at least one of the cells, or (B) changing locations correspondingly of at least two of the cells.
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公开(公告)号：US20170039310A1
公开(公告)日：2017-02-09
申请号：US15299711
申请日：2016-10-21
发明人： Chung-Hsing WANG , King-Ho TAM , Yen-Pin CHEN , Wen-Hao CHEN , Chung-Kai LIN , Chih-Hsiang YAO
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5009 , G06F17/5081
摘要： A method of designing a circuit includes designing a first layout of the circuit based on a first plurality of corner variation values for an electrical characteristic of a corresponding plurality of back end of line (BEOL) features of the circuit. Based on the layout, a processor calculates a first delay attributable to the plurality of BEOL features and a second delay attributable to a plurality of front end of line (FEOL) devices of the circuit. If the first delay is greater than the second delay, a second layout of the circuit is designed based on a second plurality of corner variation values for the electrical characteristic of the corresponding plurality of BEOL features. Each corner variation value of the first plurality of corner variation values is obtained by multiplying a corresponding corner variation value of the second plurality of corner variation values by a corresponding scaling factor.
摘要翻译： 一种设计电路的方法包括基于电路的相应多个后端（BEOL）特征的电特性的第一多个角变化值来设计电路的第一布局。 基于布局，处理器计算归因于多个BEOL特征的第一延迟和归因于电路的多个前端（FEOL）设备的第二延迟。 如果第一延迟大于第二延迟，则基于对应的多个BEOL特征的电特性的第二多个角变化值来设计电路的第二布局。 通过将第二多个角度变化值的对应拐角变化值乘以相应的缩放因子来获得第一多个角度变化值的每个角度变化值。
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公开(公告)号：US20160232270A1
公开(公告)日：2016-08-11
申请号：US14615084
申请日：2015-02-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises processing a layout of an integrated circuit to determine one or more attributes of one or more components of the integrated circuit. The method also comprises extracting one or more process parameters from a process file associated with manufacturing the integrated circuit. The one or more process parameters are extracted from the process file based on a computation of one or more logic functions included in the process file. The computation is based on the one or more attributes. The method further comprises calculating a capacitance value between at least two components of the integrated circuit based on the one or more process parameters and a capacitance determination rule included in the process file. At least one of the one or more process parameters, the one or more logic functions, or the capacitance determination rule is editable based on a user input.
摘要翻译： 一种方法包括处理集成电路的布局以确定集成电路的一个或多个组件的一个或多个属性。 该方法还包括从与制造集成电路相关联的处理文件中提取一个或多个处理参数。 基于包括在处理文件中的一个或多个逻辑功能的计算，从处理文件中提取一个或多个处理参数。 计算基于一个或多个属性。 该方法还包括基于一个或多个处理参数和包括在处理文件中的电容确定规则来计算集成电路的至少两个分量之间的电容值。 一个或多个处理参数，一个或多个逻辑功能或电容确定规则中的至少一个可以基于用户输入进行编辑。
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公开(公告)号：US20150278427A1
公开(公告)日：2015-10-01
申请号：US14231200
申请日：2014-03-31
发明人： Shyh-Horng YANG , Chung-Kai LIN , Chung-Hsing WANG , Kuo-Nan YANG , Shou-En LIU , Jhong-Sheng WANG , Tan-Li CHOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/80
摘要： A method of designing a circuit includes receiving a circuit design, and determining a temperature change of at least on back end of line (BEOL) element of the circuit design. The method further includes identifying at least one isothermal region within the circuit design; and determining, using a processor, a temperature increase of at least one front end of line (FEOL) device within the at least one isothermal region. The method further includes combining the temperature change of the at least one BEOL element with the temperature change of the at least one FEOL device, and comparing the combined temperature change with a threshold value.
摘要翻译： 一种设计电路的方法包括接收电路设计，并确定电路设计的至少后端（BEOL）元件的温度变化。 该方法还包括识别电路设计内的至少一个等温区域; 以及使用处理器确定所述至少一个等温区域内的至少一个前端（FEOL）装置的温度升高。 该方法还包括将至少一个BEOL元件的温度变化与至少一个FEOL装置的温度变化组合，以及将组合的温度变化与阈值进行比较。
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公开(公告)号：US20240201727A1
公开(公告)日：2024-06-20
申请号：US18429995
申请日：2024-02-01
发明人： Jerry Chang Jui KAO , Huang-Yu CHEN , Sheng-Hsiung CHEN , Jack LIU , Yung-Chen CHIEN , Wei-Hsiang MA , Chung-Hsing WANG
IPC分类号： G06F1/10 , G06F30/396
CPC分类号： G06F1/10 , G06F30/396
摘要： A clock distribution system includes a clock mesh structure which has first metal patterns extending along a first axis, second metal patterns extending along a second axis, third metal patterns extending along a third axis. The first metal patterns, second metal patterns, and third metal patterns are electrically coupled with each other. The second axis is transverse to the first axis. The third axis is oblique to both the first axis and the second axis. The first metal patterns include a main first metal pattern, and other first metal patterns. The second metal patterns include a main second metal pattern, and other second metal patterns. The third metal patterns include a main third metal pattern, and other third metal patterns. The main third metal pattern overlaps the main first metal pattern and the main second metal pattern, without overlapping the other first metal patterns or the other second metal patterns
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公开(公告)号：US20230401370A1
公开(公告)日：2023-12-14
申请号：US18446739
申请日：2023-08-09
发明人： Chin-Shen LIN , Hiranmay BISWAS , Kuo-Nan YANG , Chung-Hsing WANG
IPC分类号： G06F30/392
CPC分类号： G06F30/392 , G06F2119/06
摘要： A method executed at least partially by a processor includes determining a power parameter associated with a cell in an integrated circuit (IC) layout diagram. In response to the determined power parameter exceeding a design criterion, the method further includes performing a modification of the IC layout diagram, the modification including at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell. The determining the power parameter is performed before a routing operation in the IC layout diagram.
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