公开(公告)号：US09496222B2

公开(公告)日：2016-11-15

申请号：US14173906

申请日：2014-02-06

Applicant: FUJITSU LIMITED

Inventor： Junichi Kon ,  Yoshihiro Nakata ,  Kozo Makiyama

IPC: H01L23/52 ,  H01L23/532 ,  H01L23/522 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/285 ,  H01L29/20

CPC classification number: H01L23/5329 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/0272 ,  H01L21/0331 ,  H01L21/28587 ,  H01L23/5222 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture.

Abstract translation: 半导体器件具有包括基板，形成在基板的主平面的一部分上的第一绝缘膜，形成在第一绝缘膜的表面上的导电部分和覆盖第一绝缘膜的主平面的第二绝缘膜的结构 基板，第一绝缘膜和导电部分，并且其耐湿性高于第一绝缘膜的耐湿性。 第一绝缘膜被放置在基板和导电部分之间以防止寄生电容的产生。 第一绝缘膜被第一绝缘膜的耐湿性高于第一绝缘膜的第二绝缘膜覆盖。 第二绝缘膜防止第一绝缘膜吸收水分。

公开(公告)号：US09484446B2

公开(公告)日：2016-11-01

申请号：US14808670

申请日：2015-07-24

Applicant: Sumitomo Electric Device Innovations, Inc.

Inventor： Masahiro Nishi

IPC: H01L21/285 ,  H01L29/423 ,  H01L29/778 ,  H01L29/20 ,  H01L29/47

CPC classification number: H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475

Abstract: A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity.

公开(公告)号：US09449833B1

公开(公告)日：2016-09-20

申请号：US14101102

申请日：2013-12-09

Applicant: HRL LABORATORIES, LLC.

Inventor： Dean C. Regan ,  Keisuke Shinohara ,  Yan Tang ,  Miroslav Micovic

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/28587 ,  H01L21/28114 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7783

Abstract: A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material.

Abstract translation: 用于定位T形栅极的茎相对于FET或HEMT的源极和漏极接触的自对准工艺。 门杆在一些实施例中是不对称的，并且在这种实施例中，通过形成多个侧壁间隔件，T形门的杆相对于器件的漏极和源极接触定位，在漏极侧形成更多的侧壁间隔物 的茎比在茎的源侧形成。 此外，门极优选地具有高纵横比以改善所得FET或HEMT的性能。 漏极和源极触点优选由n +半导体材料形成。

公开(公告)号：US09406758B2

公开(公告)日：2016-08-02

申请号：US14738906

申请日：2015-06-14

Applicant: Iman Rezanezhad Gatabi

Inventor： Iman Rezanezhad Gatabi

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/15 ,  H01L29/8605 ,  H01L29/872 ,  H01L29/205 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417

CPC classification number: H01L29/2003 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/155 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/423 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/8605 ,  H01L29/872

Abstract: This application discloses semiconductor devices with sharp gate edges including 2D and 3D memory cells, High Electron Mobility Transistors and tri-gate transistors. Implementation of a gate with sharp edges may improve the read and write speed and reduce the program and erase voltages in memory cells. It may also improve the gate control over the channel in tri-gate transistors and HEMTs. Methods to fabricate such devices are also disclosed.

Abstract translation: 本申请公开了具有尖锐的栅极边缘的半导体器件，包括2D和3D存储器单元，高电子迁移率晶体管和三栅极晶体管。 实现具有尖锐边沿的栅极可以提高读取和写入速度，并减少存储器单元中的编程和擦除电压。 它还可以改善三栅晶体管和HEMT中的沟道上的栅极控制。 还公开了制造这种装置的方法。

公开(公告)号：US20160155684A1

公开(公告)日：2016-06-02

申请号：US15014929

申请日：2016-02-03

Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.

Inventor： CHANG-MING LIN ,  YU-JUAN TAO

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/485 ,  H01L21/28 ,  H01L21/28587 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/3192 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/48 ,  H01L23/482 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06102 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13541 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/14051 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17106 ,  H01L2224/17519 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/831 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L21/304 ,  H01L21/78 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals.

Abstract translation: 提供半导体封装方法。 该方法包括提供半导体衬底。 半导体衬底具有第一表面和第二表面，以及在半导体衬底的第一表面上的电镀籽晶层。 该方法还包括在电镀种子层上形成多个柱状电极，其中柱状电极包括第一柱状电极和第二柱状电极。 此外，该方法包括在第一柱状电极和第二柱状电极上形成扩散阻挡层，在第一柱状电极上的扩散阻挡层上形成多个第一焊球。 该方法还包括提供具有对应于第一焊球的焊接端子的封装基板，并将半导体基板安装在翻转位置的封装基板上，使得第一焊球与焊接端子连接。

公开(公告)号：US09281204B2

公开(公告)日：2016-03-08

申请号：US14259813

申请日：2014-04-23

Applicant: Freescale Semiconductor, Inc.

Inventor： Karen E. Moore ,  Bruce M. Green

IPC: H01L21/461 ,  H01L21/285 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L21/28587 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device is provided which includes a GaN-on-SiC substrate (50-51) and a multi-layer passivation stack (52-54) in which patterned step openings (76) are defined and filled with gate metal layers using a lift-off gate metal process to form a T-gate electrode (74) as a stepped gate electrode having sidewall extensions and a contact base portion with one or more gate ledges.

Abstract translation: 提供了一种半导体器件，其包括SiC-SiC衬底（50-51）和多层钝化堆叠（52-54），其中图案化的步骤开口（76）被限定并且使用电梯填充有栅极金属层 以形成具有侧壁延伸部的阶梯状栅电极的T形栅电极（74）和具有一个或多个栅极突起的接触基部。

公开(公告)号：US09276077B2

公开(公告)日：2016-03-01

申请号：US13898580

申请日：2013-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/778 ,  H01L21/285 ,  H01L29/20

CPC classification number: H01L29/45 ,  H01L21/28575 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/778

Abstract: A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the Group IIIA element to form locally doped regions underneath the source region and the drain region. Ohmic contacts may be formed at a temperature as low as about 500° C. This enables fabrication of FET whose source and drain are self-aligned to the gate.

Abstract translation: 采用采用第一难熔金属阻挡层，IIIA族元素层，第二难熔金属阻挡层和抗氧化金属层的金属化方案来形成向化合物半导体提供电接触的源区和漏区 材料层。 第一和第二难熔金属阻挡层没有氮，因此不会在化合物半导体层中引入额外的氮，同时允许IIIA族元素的扩散以在源极区域和漏极区域下方形成局部掺杂区域。 欧姆接触可以在低至约500℃的温度下形成。这使得能够制造其源极和漏极与栅极自对准的FET。

公开(公告)号：US09171920B2

公开(公告)日：2015-10-27

申请号：US14180714

申请日：2014-02-14

Applicant: National Chiao Tung University

Inventor： Yi Chang ,  Chien-I Kuo ,  Heng-Tung Hsu

IPC: H01L29/423 ,  H01L29/778 ,  H01L29/66 ,  H01L21/285 ,  H01L21/28

CPC classification number: H01L29/42316 ,  H01L21/28 ,  H01L21/28587 ,  H01L29/4232 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7784

Abstract: The present invention discloses a gate structure, which is applied for an electronic component comprising a substrate and an active region defined thereon, and such the gate structure is disposed in the active region and is a T-shaped gate having a stem with a height of 250 nm. Preferably, the gate structure has a gate length of 60 nm.

Abstract translation: 本发明公开了一种门结构，其应用于包括基板和限定在其上的有源区域的电子部件，并且这种栅极结构设置在有源区域中，并且是T形栅极，其具有高度为 250 nm。 优选地，栅极结构的栅极长度为60nm。

公开(公告)号：US20150295072A1

公开(公告)日：2015-10-15

申请号：US14327559

申请日：2014-07-09

Applicant: Iman Rezanezhad Gatabi

Inventor： Iman Rezanezhad Gatabi

IPC: H01L29/778 ,  H01L29/872 ,  H01L21/285 ,  H01L29/205 ,  H01L29/16 ,  H01L29/8605 ,  H01L29/66

CPC classification number: H01L29/2003 ,  H01L21/28587 ,  H01L29/0657 ,  H01L29/1029 ,  H01L29/155 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/423 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/8605 ,  H01L29/872

Abstract: Three methods will be described which may be used to improve the performance of compound semiconductor devices and Field Effect Transistors. In the first method, implementation of more than one sheet of 2DEG or high-density electrons in compound semiconductor devices will be described which may be used to improve the performance of compound semiconductor diodes, resistors and transistors. In the second method, implementation of at least one discontinuity in sheet or sheets of 2DEG or high-density electrons will be discussed which can be used to improve the performance of compound semiconductor diodes, resistors and transistors. In the third method, a way to form an electrical connection between an electrode and a sheet of 2DEG or high density electrons will be presented which may be implemented in compound semiconductor devices to reduce the contact resistance between an electrode and a sheet of 2DEG or high-density electrons.

Abstract translation: 将描述可用于改善化合物半导体器件和场效应晶体管的性能的三种方法。 在第一种方法中，将描述可以用于提高化合物半导体二极管，电阻器和晶体管的性能的多于一张2DEG或高密度电子的化合物半导体器件的实现。 在第二种方法中，将讨论可以用于改进化合物半导体二极管，电阻器和晶体管的性能的2DEG或高密度电子的片或片的至少一个不连续性的实现。 在第三种方法中，将提出在电极和2DEG或高密度电子片之间形成电连接的方法，其可以在化合物半导体器件中实现，以减少电极和2DEG或高电极片之间的接触电阻 密度电子。

公开(公告)号：US09123792B2

公开(公告)日：2015-09-01

申请号：US14226454

申请日：2014-03-26

Applicant: Sumitomo Electric Device Innovations, Inc.

Inventor： Masahiro Nishi

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/285 ,  H01L29/47 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475

Abstract: A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity.

Abstract translation: 半导体器件包括：氮化物半导体层; 在氮化物半导体层上形成的第一氮化硅膜具有内壁为前锥形的第一开口部， 形成在所述第一氮化硅膜上的第二氮化硅膜，并且具有内壁为反锥形形状的第二开口; 以及栅电极，其形成为覆盖暴露在所述第一开口内侧的所述氮化物半导体层的整个表面; 其中所述栅电极的侧壁经由空腔与所述第一氮化硅膜和所述第二氮化硅膜分离。