公开(公告)号：US09666684B2

公开(公告)日：2017-05-30

申请号：US13945281

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/66462 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/7784 ,  H01L29/78

Abstract: A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.

公开(公告)号：US09276077B2

公开(公告)日：2016-03-01

申请号：US13898580

申请日：2013-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/778 ,  H01L21/285 ,  H01L29/20

CPC classification number: H01L29/45 ,  H01L21/28575 ,  H01L21/28587 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/778

Abstract: A metallization scheme employing a first refractory metal barrier layer, a Group IIIA element layer, a second refractory metal barrier layer, and an oxidation-resistant metallic layer is employed to form a source region and a drain region that provide electrical contacts to a compound semiconductor material layer. The first and second refractory metal barrier layer are free of nitrogen, and thus, do not introduce additional nitrogen into the compound semiconductor layer, while allowing diffusion of the Group IIIA element to form locally doped regions underneath the source region and the drain region. Ohmic contacts may be formed at a temperature as low as about 500° C. This enables fabrication of FET whose source and drain are self-aligned to the gate.

Abstract translation: 采用采用第一难熔金属阻挡层，IIIA族元素层，第二难熔金属阻挡层和抗氧化金属层的金属化方案来形成向化合物半导体提供电接触的源区和漏区 材料层。 第一和第二难熔金属阻挡层没有氮，因此不会在化合物半导体层中引入额外的氮，同时允许IIIA族元素的扩散以在源极区域和漏极区域下方形成局部掺杂区域。 欧姆接触可以在低至约500℃的温度下形成。这使得能够制造其源极和漏极与栅极自对准的FET。

公开(公告)号：US09431494B2

公开(公告)日：2016-08-30

申请号：US14739137

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/28 ,  H01L21/283 ,  H01L29/10 ,  H01L29/201 ,  H01L29/417

CPC classification number: H01L29/42356 ,  H01L21/28026 ,  H01L21/283 ,  H01L29/1054 ,  H01L29/201 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

公开(公告)号：US20160099329A1

公开(公告)日：2016-04-07

申请号：US14968061

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/423 ,  H01L21/31 ,  H01L21/306 ,  H01L21/768 ,  H01L21/265 ,  H01L21/3105 ,  H01L29/417 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

公开(公告)号：US09231094B2

公开(公告)日：2016-01-05

申请号：US13898585

申请日：2013-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Bahman Hekmatshoartabari ,  Davood Shahrjerdi

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/283 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01L29/7786 ,  H01L21/0272 ,  H01L21/283 ,  H01L21/31144 ,  H01L29/0843 ,  H01L29/207 ,  H01L29/267 ,  H01L29/401 ,  H01L29/42316 ,  H01L29/456 ,  H01L29/475 ,  H01L29/66431 ,  H01L29/66462

Abstract: Portions of a top compound semiconductor layer are recessed employing a gate electrode as an etch mask to form a source trench and a drain trench. A low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material in the source trench and the drain trench. Metallization is performed on physically exposed surfaces of the elemental semiconductor material portions in the source trench and the drain trench by depositing a metal and inducing interaction with the metal and the at least one elemental semiconductor material. A metal semiconductor alloy of the metal and the at least one elemental semiconductor material can be performed at a temperature lower than 600° C. to provide a high electron mobility transistor with a well-defined device profile and reliable metallization contacts.

Abstract translation: 使用栅电极作为蚀刻掩模来凹陷顶部化合物半导体层的部分以形成源极沟槽和漏极沟槽。 采用低温外延工艺在源极沟槽和漏极沟槽中沉积包括至少一种元素半导体材料的半导体材料。 通过沉积金属并诱导与金属和至少一种元素半导体材料的相互作用，在源沟槽和漏极沟槽中的元素半导体材料部分的物理暴露的表面上进行金属化。 可以在低于600℃的温度下进行金属和至少一种元素半导体材料的金属半导体合金，以提供具有良好限定的器件轮廓和可靠的金属化接触的高电子迁移率晶体管。

公开(公告)号：US09224866B2

公开(公告)日：2015-12-29

申请号：US14010589

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anirban Basu ,  Guy Cohen ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31055 ,  H01L21/76802 ,  H01L21/76879 ,  H01L29/41733 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor fin including a vertical stack, from bottom to top, of a second semiconductor material and a first semiconductor material is formed on a substrate. A disposable gate structure straddling the semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask, At least one semiconductor shell layer or a semiconductor cap layer can be formed as an etch stop structure. A planarization dielectric layer is subsequently formed. A gate cavity is formed by removing the disposable gate structure. A portion of the second semiconductor material is removed selective to the first semiconductor material within the gate cavity so that a middle portion of the semiconductor fin becomes suspended over the substrate. A gate dielectric layer and a gate electrode are sequentially formed. The gate electrode laterally surrounds a body region of a fin field effect transistor.

Abstract translation: 在基板上形成包括第二半导体材料和第一半导体材料的从底部到顶部的垂直叠层的半导体鳍片。 形成跨越半导体鳍片的一次性栅极结构。 使用一次性栅极结构作为注入掩模形成源区和漏区，可以形成至少一个半导体外壳层或半导体盖层作为蚀刻停止结构。 随后形成平坦化介电层。 通过去除一次性栅极结构形成栅极腔。 第二半导体材料的一部分被选择性地移除到栅极腔内的第一半导体材料，使得半导体鳍片的中间部分悬浮在衬底上。 依次形成栅介质层和栅电极。 栅电极横向围绕鳍场效应晶体管的体区。