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公开(公告)号:US09711648B1
公开(公告)日:2017-07-18
申请号:US15232164
申请日:2016-08-09
Applicant: GLOBALFOUNDRIES INC.
Inventor: Effendi Leobandung , Chung-Hsun Lin , Amlan Majumdar , Yanning Sun
IPC: H01L29/786 , H01L29/66 , H01L29/78
CPC classification number: H01L29/78603 , H01L21/84 , H01L21/845 , H01L27/1203 , H01L27/1211 , H01L29/66522 , H01L29/66651 , H01L29/66795 , H01L29/785 , H01L29/78681 , H01L29/78696
Abstract: A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.
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公开(公告)号:US09508640B2
公开(公告)日:2016-11-29
申请号:US13940874
申请日:2013-07-12
Applicant: GLOBALFOUNDRIES INC.
Inventor: Cheng-Wei Cheng , Szu-Lin Cheng , Keith E. Fogel , Edward W. Kiewra , Amlan Majumdar , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
IPC: H01L21/00 , H01L23/522 , H01L23/485 , H01L21/8238 , H01L27/12
CPC classification number: H01L23/5226 , H01L21/823807 , H01L21/823878 , H01L23/485 , H01L27/1207 , H01L2924/0002 , H01L2924/00
Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.
Abstract translation: 用于形成具有多层接触结构的器件的方法包括将通孔中的第一触点形成为第一级,在第一触点的暴露部分上形成电介质覆盖层,并在覆盖层上形成电介质层。 通孔在电介质层中向下开到封盖层。 孔通过通孔在封盖层中打开以露出第一触点。 接触连接器和第二触点形成在通孔中,使得第一和第二触点通过接触连接器通过覆盖层连接以形成多层接触。
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公开(公告)号:US09337281B2
公开(公告)日:2016-05-10
申请号:US14803910
申请日:2015-07-20
Applicant: GLOBALFOUNDRIES INC.
Inventor: Cheng-Wei Cheng , Jack O. Chu , Devendra K. Sadana , Kuen-Ting Shiu , Yanning Sun
IPC: H01L21/336 , H01L29/267 , H01L29/772 , H01L29/45 , H01L21/02 , H01L21/285 , H01L21/322 , H01L29/66 , H01L29/78
CPC classification number: H01L29/267 , H01L21/02387 , H01L21/02439 , H01L21/02532 , H01L21/02538 , H01L21/0262 , H01L21/02661 , H01L21/02664 , H01L21/28575 , H01L21/3228 , H01L29/452 , H01L29/66522 , H01L29/772 , H01L29/78
Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.
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公开(公告)号:US09666684B2
公开(公告)日:2017-05-30
申请号:US13945281
申请日:2013-07-18
Applicant: GLOBALFOUNDRIES INC.
Inventor: Anirban Basu , Amlan Majumdar , Yanning Sun
IPC: H01L29/78 , H01L29/66 , H01L29/778 , H01L29/205 , H01L29/417 , H01L29/423
CPC classification number: H01L29/66462 , H01L29/205 , H01L29/41775 , H01L29/4236 , H01L29/7784 , H01L29/78
Abstract: A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.
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