公开(公告)号：US09379058B2

公开(公告)日：2016-06-28

申请号：US14274184

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Ohsang Kwon ,  Kern Rim ,  John Jianhong Zhu ,  Xiangdong Chen ,  Foua Vang ,  Raymond George Stephany ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/768 ,  H01L27/118

CPC classification number: H01L23/5283 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/41775 ,  H01L29/42312 ,  H01L2027/11866 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.

Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。

公开(公告)号：US20160163714A1

公开(公告)日：2016-06-09

申请号：US14559258

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

Abstract translation: 公开了在SRAM位单元的边界边缘分割的具有字线着色焊盘的静态随机存取存储器（SRAM）位单元。 一方面，公开了在第二金属层中采用写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线具有更宽的宽度，这降低了字线电阻，减少了访问时间，并且提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨道。 为了将读取字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在SRAM位单元的边界内部和外部的对应轨道上。 对应于写入字线的着陆焊盘被放置在SRAM位单元的边界边缘内的对应的轨道上。

公开(公告)号：US09349686B2

公开(公告)日：2016-05-24

申请号：US14206360

申请日：2014-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

Abstract translation: 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

公开(公告)号：US20160140275A1

公开(公告)日：2016-05-19

申请号：US14656426

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Kern Rim ,  Choh Fei Yeap

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F15/76

Abstract: A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are based on the first usage conditions and the second usage conditions.

Abstract translation: 一种用于设计用于无线设备的片上系统（SOC）的方法包括：在设计处理器处接收所述SOC的第一模块的第一使用条件和所述SOC的第二模块的第二使用条件。 该方法还包括确定SOC的设计参数。 设计参数基于第一使用条件和第二使用条件。

公开(公告)号：US20160126144A1

公开(公告)日：2016-05-05

申请号：US14991882

申请日：2016-01-08

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Kern Rim ,  John Jianhong Zhu ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L21/823814 ,  C23C14/24 ,  C23C14/54 ,  C23C16/46 ,  C23C16/52 ,  H01L21/285 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66568

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

公开(公告)号：US09318564B2

公开(公告)日：2016-04-19

申请号：US14281710

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: H01L29/76 ,  H01L29/40 ,  H01L29/161 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

Abstract translation: 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二相对侧对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。

公开(公告)号：US09257556B2

公开(公告)日：2016-02-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Vladimir Machkaoutsan ,  Kern Rim ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US09159576B2

公开(公告)日：2015-10-13

申请号：US13784867

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  H01L21/32

CPC classification number: H01L21/3085 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66795

Abstract: A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.

Abstract translation: 在由衬底形成的绝缘体上硅（SOI）晶片，衬底上的底部氧化物层和底部氧化物层上的活性硅层上进行方法，其中活性硅层具有与底部氧化物相对的表面 层。 该方法包括在晶片的第一部分处在表面上形成第一掩模，并且离开晶片的第二部分未被屏蔽，在晶片的未屏蔽的第二部分处蚀刻晶片以在有源硅层中形成凹陷，凹陷 具有底部，形成基本上填充凹陷的热氧化层，去除第一掩模，以及在晶片的第一和第二部分处形成翅片。

公开(公告)号：US20140252474A1

公开(公告)日：2014-09-11

申请号：US13784867

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song

IPC: H01L21/84 ,  H01L29/06 ,  H01L21/308 ,  H01L27/12

CPC classification number: H01L21/3085 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/32 ,  H01L21/76205 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/66795

Abstract: A method is performed on a silicon-on-insulator (SOI) wafer formed of a substrate, a bottom oxide layer on the substrate and an active silicon layer on the bottom oxide layer, where the active silicon layer has a surface opposite the bottom oxide layer. The method includes forming a first mask over the surface at a first portion of the wafer and leaving a second portion of the wafer unmasked, etching the wafer at the unmasked second portion of the wafer to form a depression in the active silicon layer, the depression having a bottom, forming a thermal oxide layer substantially filling the depression, removing the first mask, and forming fins at the first and second portions of the wafer.

Abstract translation: 在由衬底形成的绝缘体上硅（SOI）晶片，衬底上的底部氧化物层和底部氧化物层上的活性硅层上进行方法，其中活性硅层具有与底部氧化物相对的表面 层。 该方法包括在晶片的第一部分处在表面上形成第一掩模，并且离开晶片的第二部分未被屏蔽，在晶片的未屏蔽的第二部分处蚀刻晶片以在有源硅层中形成凹陷，凹陷 具有底部，形成基本上填充凹陷的热氧化层，去除第一掩模，以及在晶片的第一和第二部分处形成翅片。

公开(公告)号：US20230317677A1

公开(公告)日：2023-10-05

申请号：US17657760

申请日：2022-04-04

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jonghae Kim ,  Je-Hsiung Lan ,  Periannan Chidambaram

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/20 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/481 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/76898 ,  H01L24/19 ,  H01L25/50 ,  H01L2224/214 ,  H01L2225/06541 ,  H01L2225/06558

Abstract: Three-dimensional (3D) integrated circuit (IC) (3DIC) package employing a redistribution layer (RDL) interposer facilitating semiconductor die (“die”), and related fabrication methods. The 3DIC package includes an RDL interposer that has one or more RDL metallization layers formed adjacent to a first, bottom die(s). A second, top die(s) is stacked on the RDL interposer. The RDL interposer provides an extended die area that the top die can be coupled so that the fabrication process of the 3DIC package is independent die sizes. The bottom die(s) can be singulated and disposed in an RDL metallization layer(s) as part of a reconstituted RDL interposer regardless of whether the top die(s) is greater than or less than the size of the bottom die(s). Also, the RDL interposer being the substrate in which the bottom die(s) is disposed and top die(s) is coupled provides efficient signal routing paths to the top and bottom dies.