公开(公告)号：US20240105724A1

公开(公告)日：2024-03-28

申请号：US18196741

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  MYUNGIL KANG ,  MINCHAN GWAK ,  Kyungho KIM ,  Kyung Hee CHO ,  DOYOUNG CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact coupled to the lower contact, and a second active contact coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.

公开(公告)号：US20240105614A1

公开(公告)日：2024-03-28

申请号：US17954979

申请日：2022-09-28

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Koichi Motoyama ,  Feng Liu

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor structure includes a first via-to-backside power rail having a lower portion and an upper portion. The lower portion is connected to a first backside power rail and has a first width and the upper portion has a second width less than the first width.

公开(公告)号：US20240105452A1

公开(公告)日：2024-03-28

申请号：US17952695

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Matthew J. Prince ,  Alison V. Davis ,  Chun C. Kuo ,  Andrew Arnold ,  Ramy Ghostine ,  Li Huey Tan

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.

公开(公告)号：US11942548B2

公开(公告)日：2024-03-26

申请号：US17302987

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Carlos H. Diaz ,  Chih-Hao Wang ,  Wai-Yi Lien ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

公开(公告)号：US11942523B2

公开(公告)日：2024-03-26

申请号：US18168422

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Pei-Yu Wang ,  Chi On Chui

IPC: H01L29/417 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7834 ,  H01L29/78696 ,  H01L21/30604 ,  H01L21/3065

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

公开(公告)号：US11942516B2

公开(公告)日：2024-03-26

申请号：US17704906

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Hubert C. George ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/324 ,  H01L23/46 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/43 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/78 ,  H01L29/82

CPC classification number: H01L29/127 ,  B82Y10/00 ,  G06N10/00 ,  H01L21/28158 ,  H01L23/46 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/423 ,  H01L29/42312 ,  H01L29/42364 ,  H01L29/437 ,  H01L29/66439 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7831 ,  H01L29/7845 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/324 ,  H01L29/66431 ,  H01L29/778 ,  H01L29/7782 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a first gate above the quantum well stack, wherein the first gate includes a first gate metal and a first gate dielectric; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal and a second gate dielectric, and the first gate is at least partially between a portion of the second gate and the quantum well stack.

公开(公告)号：US20240096979A1

公开(公告)日：2024-03-21

申请号：US18152938

申请日：2023-01-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun HUANG

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/28123 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66439 ,  H01L29/775

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate. The fin structure includes alternately stacked first semiconductor material layers and second semiconductor material layers. The method includes forming a spacer layer over the fin structure. The method includes forming a first inter-layer dielectric (ILD) layer over the spacer layer. The method also includes recessing the fin structure and the first ILD layer to form a first opening through the first ILD layer. The method further includes forming an epitaxial structure in the first opening, and forming a second ILD layer over the epitaxial structure and the first ILD layer. In addition, the method includes removing the first semiconductor material layers, and forming a gate structure around the second semiconductor material layers.

公开(公告)号：US20240096947A1

公开(公告)日：2024-03-21

申请号：US17933882

申请日：2022-09-21

Applicant: International Business Machines Corporation

Inventor： Kirsten Emilie Moselund ,  Nicolas Jean Loubet ,  Bogdan Cezar Zota ,  Shogo Mochizuki

IPC: H01L29/06 ,  H01L21/8238 ,  H01L29/20 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/20 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of the present invention are directed to the implantation of composite tunnel field effect transistors (TFETs) in a nanosheet process. In a non-limiting embodiment of the invention, a first source or drain region is formed having a first composition and a first doping type. A second source or drain region is formed having a second composition and a second doping type opposite the first doping type. A first composite channel structure is formed between the first source or drain region and the second source or drain region. The first composite channel structure includes a first nanosheet trimmed to expose extension portions of the first source or drain region and extension portions of the second source or drain region. The first composite channel structure further includes a first channel epitaxy wrapping around the trimmed first nanosheet. The first channel epitaxy is connected laterally to the extension portions.

公开(公告)号：US20240096879A1

公开(公告)日：2024-03-21

申请号：US18298678

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu Man HWANG ,  Sung Il PARK ,  Jin Chan YUN ,  Dong Kyu LEE

IPC: H01L27/088 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.

公开(公告)号：US20240096701A1

公开(公告)日：2024-03-21

申请号：US18172240

申请日：2023-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Ching-Wei TSAI ,  Shang-Wen CHANG ,  Yi-Hsun CHIU ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.