公开(公告)号：US20240112916A1

公开(公告)日：2024-04-04

申请号：US17936934

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Matthew J. Prince ,  Alison V. Davis ,  Chun C. Kuo ,  Andrew Arnold ,  Reza Bayati

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/02603 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a gate cut formed after the formation of source/drain contacts. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region that extends from a source region to a drain region. Conductive contacts formed over the source and drain regions along a source/drain trench. The gate structure may be interrupted with a dielectric gate cut that further extends past the gate trench and into the source/drain trench where it can cut into one or more of the contacts. The contacts are formed before the gate cut to ensure complete fill of conductive material when forming the contacts. Accordingly, a liner structure on the conductive contacts is also broken by the intrusion of the gate cut and does not extend further up or down the sidewalls of the gate cut.

公开(公告)号：US20240203739A1

公开(公告)日：2024-06-20

申请号：US18083064

申请日：2022-12-16

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Matthew J. Prince ,  Alison V. Davis ,  Chun Chen Kuo ,  Andrew Arnold ,  Cun Wen

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/66439 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include one or more wide gate cuts having a multi-layer dielectric structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, by any number of gate cuts that extend through an entire thickness of the gate structure and which include dielectric material. Some of the gate cuts may be at least 2× wider than others. Such wide gate cuts may include a first dielectric layer with a first material composition, a second dielectric layer on the first dielectric layer with a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer with a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the wide gate cut and on the third dielectric layer.

公开(公告)号：US20240105452A1

公开(公告)日：2024-03-28

申请号：US17952695

申请日：2022-09-26

Applicant: Intel Corporation

Inventor： Reza Bayati ,  Matthew J. Prince ,  Alison V. Davis ,  Chun C. Kuo ,  Andrew Arnold ,  Ramy Ghostine ,  Li Huey Tan

IPC: H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/28123 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Techniques are provided to form semiconductor devices that include one or more gate cuts having a layer of polymer material at edges of the gate cut. The polymer layer may be provided as a byproduct of the etching process used to form the gate cut recess through the gate structure, and can protect any exposed portions of the source or drain regions from certain subsequent processes. The gate structure may be interrupted between two transistors with a gate cut that extends through an entire thickness of the gate structure and includes a dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. The edges of the gate cut may be lined with a polymer layer that is also on any exposed portions of the source or drain regions that were exposed during the etching process used to form the gate cut recess.