公开(公告)号：US09472628B2

公开(公告)日：2016-10-18

申请号：US14330158

申请日：2014-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/66583 ,  H01L21/2815 ,  H01L21/31051 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor structure includes a source drain region of a first material that may fulfill contact resistance and doping requirements and an extension region of a second material with increased mobility and dopant concentration. A semiconductor device fabrication process includes forming a sacrificial dielectric portion upon a semiconductor substrate, forming a sacrificial gate stack upon the sacrificial dielectric portion, forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate, forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer, forming a replacement gate trench by removing the sacrificial gate stack, forming an extension trench by vertically removing the sacrificial dielectric portion accessible via the replacement gate trench and horizontally removing the sacrificial dielectric portion beneath the spacer, and forming an extension region of a second doped material within the extension trench.

Abstract translation: 半导体结构包括可以实现接触电阻和掺杂要求的第一材料的源极漏极区域和具有增加的迁移率和掺杂剂浓度的第二材料的延伸区域。 半导体器件制造工艺包括在半导体衬底上形成牺牲电介质部分，在牺牲绝缘部分上形成牺牲栅极堆叠，在牺牲电介质部分上形成抵靠牺牲栅极的栅极间隔物，形成第一掺杂 在半导体衬底上的材料抵靠栅极间隔物，通过去除牺牲栅极堆叠形成替换栅极沟槽，通过垂直去除可通过替代栅极沟槽访问的牺牲电介质部分并水平移除间隔物下方的牺牲电介质部分，形成延伸沟槽， 以及在所述延伸沟槽内形成第二掺杂材料的延伸区域。

公开(公告)号：US20160293772A1

公开(公告)日：2016-10-06

申请号：US15073772

申请日：2016-03-18

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation

Inventor： DEYUAN XIAO

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/78681 ,  H01L29/78684

Abstract: A method for fabricating a transistor is provided. The method includes providing a semiconductor substrate; and forming at least a nanowire suspending in the semiconductor substrate. The method also includes forming a channel layer surrounding the nanowire; and forming a contact layer surrounding the channel layer. Further, the method includes forming a trench exposing the channel layer and surrounding the channel layer in the contact layer; and forming a potential barrier layer on the bottom of the trench and surrounding the channel layer. Further, the method also includes forming a gate structure surrounding the potential barrier layer and covering portions of the contact layer; and forming a source and a drain region on the contact layer at two sides of the gate structure, respectively.

Abstract translation: 提供一种用于制造晶体管的方法。 该方法包括：提供半导体衬底; 以及形成悬浮在半导体衬底中的至少一个纳米线。 该方法还包括形成围绕纳米线的沟道层; 以及形成围绕所述沟道层的接触层。 此外，该方法包括形成暴露沟道层并围绕接触层中的沟道层的沟槽; 并在沟槽的底部形成一个势垒层，并围绕着沟道层。 此外，该方法还包括形成围绕势垒层并覆盖接触层的部分的栅极结构; 以及在栅极结构的两侧分别在接触层上形成源极和漏极区域。

公开(公告)号：US09455317B1

公开(公告)日：2016-09-27

申请号：US14748521

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/06 ,  H01L21/84 ,  H01L21/306 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02321 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76243 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a semiconductor-on-insulator wafer having a buried oxide layer. The buried oxide layer includes therein opposing etch barrier regions and a gate region between the etch barrier regions. The semiconductor device further includes at least one nanowire having a channel portion interposed between opposing source/drain portions. The channel portion is suspended in the gate region. A gate electrode is formed in the gate region, and completely surrounds all surfaces of the suspended nanowire. The buried oxide layer comprises a first electrical insulating material, and the etch barrier regions comprising a second electrical insulating material different from the first electrical insulating material.

公开(公告)号：US09443847B2

公开(公告)日：2016-09-13

申请号：US14675974

申请日：2015-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chun Hsiung Tsai ,  Yi-Fang Pai

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/167 ,  H01L21/00 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823425 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer. A gate corner of the gate structure is free of dislocation and a corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, wherein the dislocations are away from the gate corner.

Abstract translation: 集成电路包括设置在衬底上的栅极结构。 集成电路还包括设置在与栅极结构相邻的凹部上的含硅材料结构。 含硅材料结构包括第一外延层和第二外延层。 栅极结构的栅极角没有位错，并且第二外延层的离开衬底表面的角部和栅极结构的间隔物之间​​的位置包括位错，其中位错远离栅极拐角。

公开(公告)号：US20160260812A1

公开(公告)日：2016-09-08

申请号：US15153249

申请日：2016-05-12

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/417 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.

公开(公告)号：US20160260811A1

公开(公告)日：2016-09-08

申请号：US14639232

申请日：2015-03-05

Applicant: International Business Machines Corporation ,  STMicroelectronics (Crolles 2) SAS

Inventor： Ahmet S. Ozcan ,  Emmanuel Petitprez

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7838

Abstract: An aspect of the invention is directed to a silicon-on-insulator device including a silicon layer on an insulating layer on a substrate; a raised source and a raised drain on the silicon layer; a gate between the raised source and the raised drain; a first spacer separating the gate from the raised source and substantially covering a first sidewall of the gate; a second spacer separating the gate from the raised drain and substantially covering a second sidewall of the gate; and a low-k layer over the raised source, the raised drain, the gate and each of the first spacer and the second spacer; and a dielectric layer over the low-k layer.

Abstract translation: 本发明的一个方面涉及一种绝缘体上硅器件，其包括在衬底上的绝缘层上的硅层; 硅层上的凸起源和升高的漏极; 升高源和升高的漏极之间的门; 将所述栅极与所述凸起源分离并且基本上覆盖所述栅极的第一侧壁的第一间隔件; 第二间隔件，其将所述栅极与所述升高的漏极分隔开并且基本上覆盖所述栅极的第二侧壁; 以及在升高的源极上的低k层，所述升高的漏极，所述栅极以及所述第一间隔物和所述第二间隔物中的每一个; 以及在低k层上的介电层。

公开(公告)号：US20160254381A1

公开(公告)日：2016-09-01

申请号：US15152260

申请日：2016-05-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsz-Mei Kwok ,  Kun-Mu Li ,  Hsueh-Chang Sung ,  Chii-Horng Li ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L29/45 ,  H01L29/167 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/306 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/32053 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region.

公开(公告)号：US09419111B2

公开(公告)日：2016-08-16

申请号：US14748270

申请日：2015-06-24

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US20160233164A1

公开(公告)日：2016-08-11

申请号：US14994167

申请日：2016-01-13

Applicant: Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

Inventor： Jung-Hun Choi ,  Da-Il Eom ,  Sun-Jung Lee ,  Sung-Uk Jang

IPC: H01L23/535 ,  H01L29/165 ,  H01L29/16 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/41791 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

Abstract translation: 集成电路器件包括在其顶部具有凹部的源极/漏极区域，在凹部内从源极/漏极区域延伸的接触插塞以及衬在该凹部上的金属硅化物层，并且具有覆盖该凹部的底部的第一部分 接触插塞和与第一部分成一体且覆盖接触插塞侧面的下部的第二部分。 硅化物层的第二部分可以具有与硅化物层的第一部分的厚度不同的厚度。 硅化物层形成在相对低的温度下，以提供在源极/漏极区域和接触插塞之间的改进的电阻特性。

公开(公告)号：US20160204258A1

公开(公告)日：2016-07-14

申请号：US15075883

申请日：2016-03-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenichi YAMAMOTO ,  Hiromi SASAKI ,  Tomotake MORITA ,  Masashige MORITOKI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823814 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7834

Abstract: To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.