公开(公告)号：US11837456B2

公开(公告)日：2023-12-05

申请号：US17890969

申请日：2022-08-18

Applicant: Intel Corporation

Inventor： Heidi M. Meyer ,  Ahmet Tura ,  Byron Ho ,  Subhash Joshi ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/762 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H10B10/00

CPC classification number: H01L21/76224 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7854 ,  H10B10/12

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

公开(公告)号：US20230387856A1

公开(公告)日：2023-11-30

申请号：US18227236

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY

Inventor： Chia-Chung CHEN ,  Chi-Feng HUANG ,  Victor Chiang LIANG ,  Fu-Huan TSAI ,  Hsieh-Hung HSIEH ,  Tzu-Jin YEH ,  Han-Min TSAI ,  Hong-Lin CHU

IPC: H03D7/14 ,  H01L29/167 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H03D7/1441 ,  H01L29/167 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/1033 ,  H03D7/1458 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823807

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

公开(公告)号：US20230387110A1

公开(公告)日：2023-11-30

申请号：US17824936

申请日：2022-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： JHU-MIN SONG ,  CHIEN-CHIH CHOU ,  YU-CHANG JONG

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L29/66545 ,  H01L21/823431 ,  H01L21/823481

Abstract: A semiconductor structure includes a substrate, a first FET device and a second FET device. The substrate has a first region and a second region. The first FET device is in the first region, and the second FET device is in the second region. The first FET device includes a first isolation structure, a first gate electrode disposed over a portion of the first isolation structure, and a first gate dielectric layer between the substrate and the first gate electrode. The first gate dielectric layer has a first thickness. The second FET device includes a plurality of fin structures, a plurality of second isolation structures, a second gate electrode over the plurality of fin structures, and a second gate dielectric layer between the second gate electrode and the plurality of fin structures. The second gate dielectric layer has a second thickness. The second thickness is less than the first thickness.

公开(公告)号：US11824103B2

公开(公告)日：2023-11-21

申请号：US17239225

申请日：2021-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Wei Pan ,  Jen-Chih Hsueh ,  Li-Feng Chu ,  Chih-Teng Liao

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

公开(公告)号：US20230369450A1

公开(公告)日：2023-11-16

申请号：US18357509

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anhao CHENG ,  Fang-Ting KUO

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H03K19/0185 ,  H01L27/092

CPC classification number: H01L29/66484 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823857 ,  H01L27/0922 ,  H01L28/40 ,  H01L29/66492 ,  H03K19/018521 ,  H01L21/823878

Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.

公开(公告)号：US20230369387A1

公开(公告)日：2023-11-16

申请号：US18355072

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Hsiao-Lan Yang ,  Chih-Yung Lin

IPC: H01G4/228 ,  H01L21/8234 ,  H01L27/06 ,  H01L21/762 ,  H01L29/06 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3105 ,  H01L29/78

CPC classification number: H01L28/60 ,  H01L21/823481 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0629 ,  H01L21/823431 ,  H01L21/76224 ,  H01L29/0649 ,  H01L23/5226 ,  H01L21/76897 ,  H01L23/528 ,  H01L21/31053 ,  H01L29/785

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

公开(公告)号：US20230369322A1

公开(公告)日：2023-11-16

申请号：US18225139

申请日：2023-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jia-Chuan YOU ,  Shi-Ning JU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528

CPC classification number: H01L27/0886 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76885 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.

公开(公告)号：US20230361203A1

公开(公告)日：2023-11-09

申请号：US17738521

申请日：2022-05-06

Applicant: Micron Technology, Inc.

Inventor： Neng-Kuo Chen ,  Jun Zhao ,  Andrew Dennis Carswell

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/6681 ,  H01L29/66545 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886

Abstract: Apparatus and methods are disclosed, including transistors, memory devices and systems. Example transistors, memory devices, systems and methods include an inter-gate dielectric structure between adjacent gates, wherein the inter-gate dielectric structure includes a first dielectric material adjacent a fin channel, and a second dielectric material different from the first dielectric material located over the first dielectric material.

公开(公告)号：US11810860B2

公开(公告)日：2023-11-07

申请号：US17249011

申请日：2021-02-17

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Nan Wang

IPC: H01L23/532 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762 ,  H01L21/768 ,  H10B10/00 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L23/53295 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6656 ,  H01L29/66545 ,  H10B10/12 ,  H01L29/086 ,  H01L29/0878

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; and a first gate structure and doped source/drain layers on the base substrate. The doped source/drain layers are on both sides of the first gate structure. The semiconductor device further includes a dielectric layer on a surface of the base substrate. The dielectric layer covers the doped source/drain layers, and the dielectric layer contains a first trench on the doped source/drain layer. The first trench includes a first region filled by an insulation layer and a second region filled by first conductive structure under the insulation layer. A top size of the insulation layer in the first region is larger than a bottom size of the insulation layer in the first region. A maximum size of the first conductive structure in the second region is smaller than the bottom size of the insulation layer in the first region.

公开(公告)号：US20230352566A1

公开(公告)日：2023-11-02

申请号：US17732028

申请日：2022-04-28

Applicant: Micron Technology, Inc.

Inventor： Bingwu Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/108

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/7851 ,  H01L21/76843 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/10805

Abstract: A variety of applications can include devices implementing one or more fin field-effect transistors (FinFETs) with gate oxide thickness that address thicker gate oxide quality with minimum material loss in the fins of the FinFETs for high voltage devices. The gate oxides can be fabricated with thicker oxides than gate oxides of FinFETs used with capacitors in memory cells of memory arrays. These gate oxides can be formed as oxide liners by oxidation with use of a protective liner to maintain uniform composition of material for the fin during FinFET processing.