公开(公告)号：US20180061630A1

公开(公告)日：2018-03-01

申请号：US15684753

申请日：2017-08-23

申请人： Quora Technology, Inc.

发明人： Vladimir Odnoblyudov ,  Dilip Risbud ,  Ozgur Aktas ,  Cem Basceri

IPC分类号： H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/872 ,  H01L29/66 ,  H01L29/778 ,  C30B29/06 ,  C30B29/40 ,  C30B25/18

CPC分类号： H01L21/6835 ,  C30B25/183 ,  C30B29/06 ,  C30B29/406 ,  H01L21/0242 ,  H01L21/02428 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/28264 ,  H01L21/4807 ,  H01L21/762 ,  H01L29/1033 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66143 ,  H01L29/66204 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/861 ,  H01L29/8613 ,  H01L29/872 ,  H01L2221/68345 ,  H01L2221/6835

摘要： A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

公开(公告)号：US09871076B2

公开(公告)日：2018-01-16

申请号：US15091551

申请日：2016-04-05

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Eng Huat Toh ,  Xuan Anh Tran ,  Kiok Boone Elgin Quek

IPC分类号： H01L27/22 ,  H01L29/66 ,  H01L43/12 ,  H01L21/02 ,  H01L21/768 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L23/528

CPC分类号： H01L27/226 ,  G11C11/161 ,  H01L21/0257 ,  H01L21/02636 ,  H01L21/768 ,  H01L23/528 ,  H01L28/00 ,  H01L29/66234 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： Devices and methods of forming a device are disclosed. The method includes providing a substrate with a cell region. Selector units and storage units are formed within the substrate. The selector unit includes first and second bipolar junction transistors (BJTs). The selector unit includes first and second bipolar junction transistors (BJTs). A BJT includes first, second and third BJT terminals. The second BJT terminals of the first and second BJTs are coupled to or serve as a common wordline terminal. The third BJT terminal of the first BJT serves as a first bitline terminal, and the third BJT terminal of the second BJT serves as a second bitline terminal. A storage unit is disposed over the selector unit. The storage unit includes a first pinning layer which is coupled to the first BJT terminal of the first BJT, a second pinning layer which is coupled to the first BJT terminal of the second BJT, a free layer which includes an elongated member with first and second major surfaces and first and second end regions separated by a free region. The first pinning layer is coupled to the second major surface of the free layer in the first end region and the second pinning layer is coupled to the second major surface of the free layer in the second end region. A reference stack is disposed on the first major surface of the free layer in the free region. The reference stack serves as a read bitline terminal.

公开(公告)号：US20170373190A1

公开(公告)日：2017-12-28

申请号：US15688214

申请日：2017-08-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Jing Lee ,  Chi-Wen Liu

IPC分类号： H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L29/165 ,  H01L29/15 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/43

CPC分类号： H01L29/161 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/432 ,  H01L29/66431 ,  H01L29/66712 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7789 ,  H01L29/7802 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

摘要： A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.

公开(公告)号：US09853030B2

公开(公告)日：2017-12-26

申请号：US15147154

申请日：2016-05-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Mieno Fumitake ,  Jianhua Ju

IPC分类号： H01L21/70 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L27/0924 ,  H01L21/02529 ,  H01L21/0257 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7853

摘要： Various embodiments provide semiconductor devices and methods for forming the same. A first fin and a second fin are formed on a semiconductor substrate. A first dielectric layer is formed on the semiconductor substrate and has a top surface lower than a top surface of both of the first fin and the second fin. A gate structure is formed on the first dielectric layer and covering across a first portion of each of the first fin and the second fin. A second portion of the first fin on both sides of the gate structure is removed, forming a first recess. A first semiconductor layer is formed in the first recess. A second dielectric layer is formed on the first dielectric layer and the first semiconductor layer, and exposes a top surface of the second fin. A second semiconductor layer is formed on the exposed top surface of the second fin.

公开(公告)号：US20170338232A1

公开(公告)日：2017-11-23

申请号：US15432697

申请日：2017-02-14

申请人： Samsung Electronics Co., Ltd.

发明人： Sang Chul HAN ,  Do Hyung KIM ,  Tae ki HONG ,  Jin Hyuk CHOI ,  Moon Hyeong HAN

IPC分类号： H01L27/108 ,  H01L21/67 ,  H01L21/3215 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L49/02 ,  H01L21/324

CPC分类号： H01L27/10852 ,  C23C16/24 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/28556 ,  H01L21/76877 ,  H01L27/10814 ,  H01L28/90 ,  H01L28/91

摘要： A method of fabricating semiconductor device is provided. The method includes providing a substrate having a trench, plasma-ionizing a gas which comprises a deposition material precursor and a doping material precursor to respectively obtain a plasma-ionized deposition material and a plasma-ionized doping material, and depositing the plasma-ionized deposition material and the plasma-ionized doping material in the trench by applying a bias voltage to a bottom surface of the trench, wherein the bottom surface of the trench comprises a first material, and sidewalls of the trench comprise a second material different from the first material.

公开(公告)号：US09735257B2

公开(公告)日：2017-08-15

申请号：US14884277

申请日：2015-10-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Dominic J. Schepis

IPC分类号： H01L21/70 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/10

CPC分类号： H01L29/6681 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

公开(公告)号：US09722082B2

公开(公告)日：2017-08-01

申请号：US15134935

申请日：2016-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chao-Hsuing Chen ,  Ling-Sung Wang ,  Chi-Yen Lin

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/167

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02579 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66628 ,  H01L29/66636

摘要： A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.

公开(公告)号：US09716090B2

公开(公告)日：2017-07-25

申请号：US15193628

申请日：2016-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Cheng-Ta Wu ,  Cheng-Wei Chen ,  Hong-Yi Wu ,  Shiu-Ko Jangjian ,  Wei-Ming You ,  Ting-Chun Wang

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L29/788 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L29/04 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L27/0886 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/26506 ,  H01L21/28035 ,  H01L21/28088 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795

摘要： A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.

公开(公告)号：US09691632B2

公开(公告)日：2017-06-27

申请号：US14649114

申请日：2013-12-03

申请人： SILTRONIC AG ,  INTEL CORPORATION

发明人： Peter Storck ,  Norbert Werner ,  Martin Vorderwestner ,  Peter Tolchinsky ,  Irwin Yablok

IPC分类号： H01L21/322 ,  H01L29/167 ,  H01L21/02

CPC分类号： H01L21/3225 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/3221 ,  H01L29/167

摘要： An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds.

公开(公告)号：US20170170283A1

公开(公告)日：2017-06-15

申请号：US15369643

申请日：2016-12-05

申请人： IQE, PLC

发明人： Oleg Laboutin ,  Chen-Kai Kao ,  Chien-Fong Lo ,  Hugues Marchand ,  Rodney Pelzel

IPC分类号： H01L29/20 ,  H01L29/36 ,  H01L29/207 ,  H01L21/02 ,  H01L29/778 ,  H01L29/66

CPC分类号： H01L29/2003 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0257 ,  H01L21/0262 ,  H01L29/207 ,  H01L29/36 ,  H01L29/66431 ,  H01L29/7787

摘要： A III-nitride structure can include a silicon substrate, a nucleation layer over the silicon substrate, and a carbon-doped buffer layer over the nucleation layer. The carbon-doped buffer layer can include a III-nitride material and a concentration of carbon that is greater than 1×1020 cm−3. The III-nitride structure can include a III-nitride channel layer over the carbon-doped buffer layer and a III-nitride barrier layer over the III-nitride channel layer. The carbon doping to a carbon concentration greater than 1×1020 cm−3 can increase the compressive stress in the III-nitride structure.