公开(公告)号：US09634140B2

公开(公告)日：2017-04-25

申请号：US14934045

申请日：2015-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Mark S. Rodder

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285 ,  H01L21/74

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/743 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7848

Abstract: Exemplary embodiments provide methods and systems for fabricating a metal source-drain stressor in a MOS device channel having improved tensile stress. Aspects of exemplary embodiment include forming a recess in source and drain areas; forming a metal contact layer on surfaces of the recess that achieves low contact resistivity; forming a metallic diffusion barrier over the metal contact layer; forming a layer M as an intimate mixture of materials A and B that substantially fills the recess; capping the layer M with a capping layer so that layer M is fully encapsulated and the capping layer prevents diffusion of A and B; and forming a compound AxBy within the layer M via a thermal reaction resulting in a reacted layer M comprising the metal source-drain stressor.

公开(公告)号：US09613907B2

公开(公告)日：2017-04-04

申请号：US14809266

申请日：2015-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ganesh Hegde ,  Mark S. Rodder ,  Jorge A. Kittl ,  Robert C. Bowen

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

公开(公告)号：US09490323B2

公开(公告)日：2016-11-08

申请号：US14722402

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna J. Obradovic ,  Rwik Sengupta

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/092 ,  H01L29/423 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/16 ,  H01L21/8238

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/775

Abstract: A device including a stacked nanosheet field effect transistor (FET) may include a substrate, a first channel pattern on the substrate, a second channel pattern on the first channel pattern, a gate that is configured to surround portions of the first channel pattern and portions of the second channel pattern, and source/drain regions on opposing ends of the first channel pattern and second channel pattern. The first and second channel patterns may each include a respective plurality of nanosheets arranged in a respective horizontal plane that is parallel to a surface of the substrate. The nanosheets may be spaced apart from each other at a horizontal spacing distance between adjacent ones of the nanosheets. The second channel pattern may be spaced apart from the first channel pattern at a vertical spacing distance from the first channel pattern to the second channel pattern that is greater than the horizontal spacing distance.

Abstract translation: 包括堆叠的纳米片场效应晶体管（FET）的器件可以包括衬底，衬底上的第一沟道图案，第一沟道图案上的第二沟道图案，被配置为围绕第一沟道图案的部分的栅极和部分 的第二沟道图案和第一沟道图案和第二沟道图案的相对端上的源极/漏极区域。 第一和第二通道图案可以各自包括布置在平行于基板的表面的相应水平平面中的相应的多个纳米片。 纳米片可以在相邻的纳米片之间的水平间隔距离处彼此间隔开。 第二通道图案可以与第一通道图案间隔开距离第一通道图案到第二通道图案的垂直间隔距离大于水平间隔距离。

公开(公告)号：US20160071729A1

公开(公告)日：2016-03-10

申请号：US14830622

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan M. Hatcher ,  Robert C. Bowen ,  Wei-E Wang ,  Mark S. Rodder

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02474 ,  H01L21/02477 ,  H01L21/02483 ,  H01L21/02485 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/02538 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow.

Abstract translation: 示例性实施例提供了制造适用于场效应晶体管（FET）制造的纳米片结构的方法。 示例性实施方案的方面包括选择将用作纳米片结构中的通道材料的活性材料，适于活性材料的外延生长的基底和在纳米片结构的制造期间使用的牺牲材料; 在衬底上生长一叠交替的活性和牺牲材料层; 并且选择性地蚀刻牺牲材料，其中由于牺牲材料的性质，选择性蚀刻导致活性材料的剩余层具有大于1的纵横比和基本上相同的厚度和原子平滑度沿着整个横截面宽度 每个活性物质层垂直于电流。

公开(公告)号：US20150318282A1

公开(公告)日：2015-11-05

申请号：US14683926

申请日：2015-04-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mark S. Rodder ,  Borna Obradovic ,  Rwik Sengupta

IPC: H01L27/088 ,  H01L21/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/10 ,  H01L21/0257 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/08 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/423 ,  H01L29/42376

Abstract: A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.

Abstract translation: 半导体结构包括第一鳍式FET器件，其包括第一鳍片，侧壁上的第一栅极电极结构和第一鳍片的上表面，第一栅电极结构下方的第一沟道区域，第一鳍片中的第一源极和漏极区域 在第一沟道区域的相对侧上，以及第二鳍状FET器件，其包括第二鳍片，侧壁上的第二栅电极结构和第二鳍片的上表面，第二栅电极结构下方的第二沟道区域，以及第二源极和 第二鳍片的漏极区域在第二沟道区域的相对侧上。 第二栅极电极结构具有与第一栅极电极结构的第一物理栅极长度基本相同的第二物理栅极长度，并且第二finFET器件具有与第一栅极电极结构的第一有效沟道长度不同的第二有效沟道长度 第一栅电极结构。

公开(公告)号：US20230361194A1

公开(公告)日：2023-11-09

申请号：US18225028

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wei-E Wang ,  Mark S. Rodder

IPC: H01L29/51 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L29/516 ,  H01L21/823857 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78696 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/0922

Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.

公开(公告)号：US11552067B2

公开(公告)日：2023-01-10

申请号：US16853535

申请日：2020-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vassilios Gerousis ,  Rwik Sengupta ,  Joon Goo Hong ,  Kevin Traynor ,  Tanya Abaya ,  Dharmendar Palle ,  Mark S. Rodder

IPC: H01L23/528 ,  H01L27/02 ,  G06F30/392

Abstract: A semiconductor cell block includes a series of layers arranged in a stack. The layers include one or more first layers each having a first height and one or more second layers each having a second height. The second height is larger than the first height, and the second height is a non-integer multiple of the first height. The semiconductor cell block also includes a first semiconductor logic cell having a first cell height in one of the series of layers, and a second semiconductor logic cell having a second cell height in one of the series of layers. The second cell height is larger than the first cell height, and the second cell height is a non-integer value multiple of the first cell height.

公开(公告)号：US11461620B2

公开(公告)日：2022-10-04

申请号：US15806259

申请日：2017-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Borna J. Obradovic ,  Titash Rakshit ,  Rwik Sengupta ,  Joon Goo Hong ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Mark S. Rodder

IPC: G06N3/063 ,  H01L29/423 ,  H01L29/78 ,  H01L21/28

Abstract: A neuromorphic multi-bit digital weight cell configured to store a series of potential weights for a neuron in an artificial neural network. The neuromorphic multi-bit digital weight cell includes a parallel cell including a series of passive resistors in parallel and a series of gating transistors. Each gating transistor of the series of gating transistors is in series with one passive resistor of the series of passive resistors. The neuromorphic cell also includes a series of programming input lines connected to the series of gating transistors, an input terminal connected to the parallel cell, and an output terminal connected to the parallel cell.

公开(公告)号：US20210183814A1

公开(公告)日：2021-06-17

申请号：US16861029

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Mark S. Rodder ,  Vassilios Gerousis

IPC: H01L25/065 ,  H01L23/00

Abstract: A method of manufacturing a three-dimensional semiconductor device includes forming a bi-layer sacrificial stack on a top wafer and a bottom wafer each including a series of interconnects in a dielectric substrate. The bi-layer sacrificial stack includes a second sacrificial layer on a first sacrificial layer. The method also includes selectively etching the second sacrificial layers to form a first pattern of projections on the top wafer and a second pattern of projections on the bottom wafer. The first pattern of projections is configured to mesh with the second pattern of projections. The method also includes positioning the top wafer on the bottom wafer and releasing the top wafer such that engagement between the first pattern of projections and the second pattern of projections self-aligns the plurality of interconnects of the top wafer with the plurality of interconnects of the bottom wafer within a misalignment error.

公开(公告)号：US20200381414A1

公开(公告)日：2020-12-03

申请号：US16997732

申请日：2020-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wei-E Wang ,  Titash Rakshit ,  Borna J. Obradovic ,  Chris Bowen ,  Mark S. Rodder

IPC: H01L27/02 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/84 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/16 ,  H01L29/47

Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.