公开(公告)号：US20240363708A1

公开(公告)日：2024-10-31

申请号：US18769271

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei Fang

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/7851 ,  H01L27/0886

Abstract: The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

公开(公告)号：US20240363428A1

公开(公告)日：2024-10-31

申请号：US18766991

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Yu Huang ,  I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor structure includes a channel member, a gate structure disposed over the channel member, a source/drain feature connected to the channel member and adjacent to the gate structure, a source/drain contact disposed below and connected to the source/drain feature, a backside dielectric feature disposed below the channel member, and a first dielectric layer and a second dielectric layer disposed between the backside dielectric feature and the source/drain contact. The first dielectric layer includes a low-k dielectric material.

公开(公告)号：US20240363427A1

公开(公告)日：2024-10-31

申请号：US18764973

申请日：2024-07-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chieh Wu ,  Pang-Chi Wu ,  Kuo-Yi Chao ,  Mei-Yun Wang ,  Hsien-Huang Liao ,  Tung-Heng Hsieh ,  Bao-Ru Young

IPC: H01L21/8234 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L21/823475 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/66545

Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

公开(公告)号：US20240363426A1

公开(公告)日：2024-10-31

申请号：US18770349

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yu Yang ,  Yen-Ting Chen ,  Wei-Yang Lee ,  Fu-Kai Yang ,  Yen-Ming Chen

IPC: H01L21/8234 ,  H01L21/033 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823468 ,  H01L21/0337 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823864 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

公开(公告)号：US20240355816A1

公开(公告)日：2024-10-24

申请号：US18762138

申请日：2024-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL YANG MING CHIAO TUNG UNIVERSITY

Inventor： Chenming HU ,  Po-Tsang HUANG

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/12

CPC classification number: H01L27/0688 ,  H01L21/02496 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/1207

Abstract: An IC structure includes a first transistor, an interconnect structure, a dielectric layer, a polysilicon fin, and a second transistor. The first transistor is over a substrate. The interconnect structure is over the first transistor. The dielectric layer is over the interconnect structure. The polysilicon fin includes a first portion laterally extending over the dielectric layer, and a second portion extending through the dielectric layer to a metal material within the interconnect structure. The second transistor is formed on the first portion of the polysilicon fin.

公开(公告)号：US12125750B2

公开(公告)日：2024-10-22

申请号：US18118505

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hyun Lee ,  Jeong Yun Lee ,  Seung Ju Park ,  Geum Jung Seong ,  Young Mook Oh ,  Seung Soo Hong

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/785 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/6656

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction. The semiconductor device includes a first gate structure on a substrate, the first gate structure extending lengthwise in a first direction to have two long sides and two short sides, relative to each other, and including a first gate spacer; a second gate structure on the substrate, the second gate structure extending lengthwise in the first direction to have two long sides and two short sides, relative to each other, and including a second gate spacer, wherein a first short side of the second gate structure faces a first short side of the first gate structure; and a gate insulating support disposed between the first short side of the first gate structure and the first short side of the second gate structure and extending lengthwise in a second direction different from the first direction, a length of the gate insulating support in the second direction being greater than a width of each of the first gate structure and the second gate structure in the second direction.

公开(公告)号：US12119408B2

公开(公告)日：2024-10-15

申请号：US18243688

申请日：2023-09-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masahiro Watanabe ,  Mitsuo Mashiyama ,  Kenichi Okazaki ,  Motoki Nakashima ,  Hideyuki Kishida

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823475 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/1233 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78672

Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.

公开(公告)号：US12113132B2

公开(公告)日：2024-10-08

申请号：US18053021

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Chiang ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L23/528 ,  H01L23/535 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/76871 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/528 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/41791

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US12113063B2

公开(公告)日：2024-10-08

申请号：US18103210

申请日：2023-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N70/00 ,  H10N70/20 ,  H01L21/8234 ,  H10K59/00

CPC classification number: H01L27/0688 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/525 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N70/011 ,  H10N70/20 ,  H10N70/231 ,  H01L21/823475 ,  H10K59/00

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US12112988B2

公开(公告)日：2024-10-08

申请号：US18361566

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/82 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L21/823481 ,  H01L21/28518 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/76229 ,  H01L21/764 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66545

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.