公开(公告)号：US20200027895A1

公开(公告)日：2020-01-23

申请号：US16272265

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Edward CHO ,  Seok Hoon KIM ,  Myung II KANG ,  Geo Myung SHIN ,  Seung Hun LEE ,  Jeong Yun LEE ,  Min Hee CHOI ,  Jeong Min CHOI

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

公开(公告)号：US20230207559A1

公开(公告)日：2023-06-29

申请号：US18055813

申请日：2022-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NAM KYU CHO ,  Seok Hoon KIM ,  Sang Gil LEE ,  Pan Kwi PARK

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775

CPC classification number: H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775

Abstract: A semiconductor device includes a first active pattern having a first lower pattern and a first sheet pattern on the first lower pattern. First gate structures include a first gate electrode. A second active pattern includes a second lower pattern. A second sheet pattern is on the second lower pattern. Second gate structures include a second gate electrode that surrounds the second sheet pattern. A first source/drain recess is between adjacent first gate structures. A second source/drain recess is between adjacent second gate structures. A first source/drain pattern extends along the first source/drain recess. A first silicon germanium filling film is on the first silicon germanium liner. A second source/drain pattern includes a second silicon germanium liner extending along the second source/drain recess. A second silicon germanium filling film is on the second silicon germanium liner.

公开(公告)号：US20220190134A1

公开(公告)日：2022-06-16

申请号：US17460446

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEO JIN JEONG ,  Do Hyun GO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Moon Seung YANG ,  Min-Hee CHOI ,  Ryong HA

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20180138269A1

公开(公告)日：2018-05-17

申请号：US15715832

申请日：2017-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Hoon KIM ,  Hyun Jung LEE ,  Kyung Hee KIM ,  Sun Jung KIM ,  Jin Bum KIM ,  Il Gyou SHIN ,  Seung Hun LEE ,  Cho Eun LEE ,  Dong Suk SHIN

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: There is provided a semiconductor device capable of enhancing short channel effect by forming a carbon-containing semiconductor pattern in a source/drain region. The semiconductor device includes a first gate electrode and a second gate electrode spaced apart from each other on a fin-type pattern, a recess formed in the fin-type pattern between the first gate electrode and the second gate electrode, and a semiconductor pattern including a lower semiconductor film formed along a profile of the recess and an upper semiconductor film on the lower semiconductor film, wherein the lower semiconductor film includes a lower epitaxial layer and an upper epitaxial layer sequentially formed on the fin-type pattern, and a carbon concentration of the upper epitaxial layer is greater than a carbon concentration of the lower epitaxial layer.

公开(公告)号：US20230056095A1

公开(公告)日：2023-02-23

申请号：US17734564

申请日：2022-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu CHO ,  Sang Gil LEE ,  Seok Hoon KIM ,  Yong Seung KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Dong Suk SHIN ,  Si Hyung LEE ,  Yang XU

IPC: H01L29/778 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a first region and a second region, a first active pattern on the first region, a first gate structure having a first width in the first direction, on the first active pattern, a first epitaxial pattern disposed in the first active pattern on a side surface of the first gate structure, a second active pattern on the second region, a second gate structure having a second width greater than the first width in the first direction, on the second active pattern and a second epitaxial pattern disposed in the second active pattern on a side surface of the second gate structure. Each of the first epitaxial pattern and the second epitaxial pattern includes silicon germanium (SiGe), and a first Ge concentration of the first epitaxial pattern is lower than a second Ge concentration of the second epitaxial pattern.

公开(公告)号：US20200343113A1

公开(公告)日：2020-10-29

申请号：US16690498

申请日：2019-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Jun CHOI ,  Seok Hoon KIM ,  Young-Hoo KIM ,  In Gi KIM ,  Sung Hyun PARK ,  Seung Min SHIN ,  Kun Tack LEE ,  Jinwoo LEE ,  Hun Jae JANG ,  Ji Hoon CHA

IPC: H01L21/67 ,  H01L21/687 ,  B08B3/08

Abstract: A multi-chamber apparatus for processing a wafer, the apparatus including a high etch rate chamber to receive the wafer and to etch silicon nitride with a phosphoric acid solution; a rinse chamber to receive the wafer and to clean the wafer with an ammonia mixed solution; and a supercritical drying chamber to dry the wafer with a supercritical fluid.

公开(公告)号：US20190058051A1

公开(公告)日：2019-02-21

申请号：US15896277

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Tae Jin PARK ,  Jong Min LEE ,  Seok Hoon KIM ,  Dong Chan SUH ,  Jeong Ho YOO ,  Ha Kyu SEONG ,  Dong Suk SHIN

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.

公开(公告)号：US20150138197A1

公开(公告)日：2015-05-21

申请号：US14534441

申请日：2014-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Hyo YU ,  Seok Hoon KIM

IPC: G06T15/80 ,  G06T1/20 ,  G06T17/10

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T17/20

Abstract: A method for domain shading may include analyzing graphics state data, and generating all first primitives through a single-pass domain shading or generating only second primitives which are visible among the first primitives through a two-pass domain shading based on a result of the analysis.

Abstract translation: 域阴影的方法可以包括分析图形状态数据，以及通过单遍域阴影生成所有第一原语，或者仅通过基于分析结果的双遍域阴影生成第一原语中可见的第二原语 。

公开(公告)号：US20240297234A1

公开(公告)日：2024-09-05

申请号：US18661171

申请日：2024-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seo Jin JEONG ,  Do Hyun GO ,  Seok Hoon KIM ,  Jung Taek KIM ,  Pan Kwi PARK ,  Moon Seung YANG ,  Min-Hee CHOI ,  Ryong HA

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.

公开(公告)号：US20240194786A1

公开(公告)日：2024-06-13

申请号：US18531898

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Suk SHIN ,  Jung Taek KIM ,  Hyun-Kwan YU ,  Seok Hoon KIM ,  Pan Kwi PARK ,  Seo Jin JEONG ,  Nam Kyu CHO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/66545

Abstract: There is provided a semiconductor device capable of improving performance and reliability of an element. The semiconductor device includes an active pattern extending in a first direction, and a plurality of gate structures spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode extending in a second direction and a gate spacer on a sidewall of the gate electrode and a source/drain pattern disposed between adjacent gate structures. The gate structure comprises a semiconductor liner layer and a semiconductor filling layer on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion protruding in a third direction beyond an upper surface of the active pattern. A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction on the upper surface of the active pattern. The semiconductor liner layer comprises an outer surface in contact with the active pattern and an inner surface facing the semiconductor filling layer. In a plan view, the inner surface of the semiconductor liner layer comprises a concave region.