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公开(公告)号:US20220190134A1
公开(公告)日:2022-06-16
申请号:US17460446
申请日:2021-08-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SEO JIN JEONG , Do Hyun GO , Seok Hoon KIM , Jung Taek KIM , Pan Kwi PARK , Moon Seung YANG , Min-Hee CHOI , Ryong HA
IPC: H01L29/423 , H01L29/786 , H01L29/06 , H01L29/08 , H01L29/417
Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
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公开(公告)号:US20240297234A1
公开(公告)日:2024-09-05
申请号:US18661171
申请日:2024-05-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seo Jin JEONG , Do Hyun GO , Seok Hoon KIM , Jung Taek KIM , Pan Kwi PARK , Moon Seung YANG , Min-Hee CHOI , Ryong HA
IPC: H01L29/423 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/786
CPC classification number: H01L29/42392 , H01L29/0665 , H01L29/0847 , H01L29/41775 , H01L29/78696
Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.
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公开(公告)号:US20230378335A1
公开(公告)日:2023-11-23
申请号:US18076639
申请日:2022-12-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sung Keun LIM , Hyo Hoon BYEON , Do Hyun GO , Un Ki KIM , Yu Yeong JO , Jin Yeong CHO
IPC: H01L29/775 , H01L29/06 , H01L29/16 , H01L29/165 , H01L29/423 , H01L21/02 , H01L29/66
CPC classification number: H01L29/775 , H01L29/0673 , H01L29/1608 , H01L29/165 , H01L29/42392 , H01L21/02603 , H01L21/02529 , H01L21/02532 , H01L29/66068
Abstract: The present disclosure provides a semiconductor device with a multi-bridge channel field effect transistor. In some embodiments, a semiconductor device includes a substrate, an active pattern that extends in a first horizontal direction on the substrate, a first nanosheet, a second nanosheet, and a gate electrode. The first nanosheet is spaced apart from the active pattern in a vertical direction, and includes a first layer, a second layer disposed on and in contact with the first layer, and a third layer disposed on and in contact with the second layer. The first and third layers include a first material, and the second layer includes a different second material. The second nanosheet is disposed on the first nanosheet and spaced apart from the first nanosheet in the vertical direction. The gate electrode extends in a second horizontal direction on the active pattern and surrounds the first and second nanosheets.
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