公开(公告)号：US10410839B2

公开(公告)日：2019-09-10

申请号：US15606025

申请日：2017-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yil-Hyung Lee ,  Yoo-Chul Kong ,  Jong-Kyu Kim ,  Seok-Woo Nam ,  Jong-Soon Park ,  Kyoung-Sub Shin

IPC: H01L21/263 ,  H01J37/32 ,  H01J37/34

Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.

公开(公告)号：US10109532B2

公开(公告)日：2018-10-23

申请号：US15658964

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  G06F17/50

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US09385134B2

公开(公告)日：2016-07-05

申请号：US14340710

申请日：2014-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ho Min ,  Ki-Jeong Kim ,  Kyoung-Sub Shin ,  Dong-Hyun Kim

IPC: H01L23/52 ,  H01L23/48 ,  H01L27/115 ,  H01L27/02 ,  H01L21/033 ,  H01L21/3213 ,  H01L27/32

CPC classification number: H01L27/11517 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L27/0203 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/3276

Abstract: In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width.

Abstract translation: 在半导体器件中，具有单位宽度的并行的第一和第二导线从存储单元区域延伸到连接区域。 连接区域中的修剪区域包括分别连接到第一和第二导电线但是被分开的宽度远大于单位宽度的焊盘。

公开(公告)号：US11302585B2

公开(公告)日：2022-04-12

申请号：US16810937

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20180197719A1

公开(公告)日：2018-07-12

申请号：US15606025

申请日：2017-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yil-Hyung Lee ,  Yoo-Chul Kong ,  Jong-Kyu Kim ,  Seok-Woo Nam ,  Jong-Soon Park ,  Kyoung-Sub Shin

IPC: H01J37/32 ,  H01J37/34 ,  C23C14/34 ,  C23C14/50

CPC classification number: H01J37/32412 ,  H01J37/32422 ,  H01J37/3435 ,  H01J37/3438 ,  H01J2237/083 ,  H01J2237/334

Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.

公开(公告)号：US09214409B2

公开(公告)日：2015-12-15

申请号：US13786853

申请日：2013-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyuk Yoo ,  Dae-Hyun Jang ,  Yoo-Chul Kong ,  Kyoung-Sub Shin

IPC: H01L29/76 ,  H01L23/48 ,  H01L27/115

CPC classification number: H01L27/1157 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Abstract translation: 提供一种半导体器件。 半导体器件包括设置在半导体衬底上的导电图案。 设置在导电图案上并且彼此位于相同水平面的第一和第二导电线。 隔离图案设置在第一和第二导线之间。 提供穿过第一导线和导电图案的第一垂直结构。 提供穿过第二导线和导电图案的第二垂直结构。 提供穿过导电图案并与隔离图案接触的辅助图案。

公开(公告)号：US12261087B2

公开(公告)日：2025-03-25

申请号：US18491470

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L29/10 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  G06F117/12 ,  G06F119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US11830775B2

公开(公告)日：2023-11-28

申请号：US17698487

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol Kim ,  Kyoung-Sub Shin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398 ,  G06F119/12 ,  G06F117/12

CPC classification number: H01L21/823807 ,  G06F7/505 ,  G06F30/39 ,  G06F30/398 ,  H01L21/308 ,  H01L21/30608 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  G06F2117/12 ,  G06F2119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20190272979A1

公开(公告)日：2019-09-05

申请号：US16413854

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yil-Hyung Lee ,  Yoo-Chul Kong ,  Jong-Kyu Kim ,  Seok-Woo Nam ,  Jong-Soon Park ,  Kyoung-Sub Shin

IPC: H01J37/32 ,  H01J37/34

Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.

公开(公告)号：US09806204B2

公开(公告)日：2017-10-31

申请号：US14536250

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Soo Ahn ,  O Ik Kwon ,  Bum-Soo Kim ,  Hyun-Sung Kim ,  Kyoung-Sub Shin ,  Min-Kyung Yun ,  Seung-Pil Chung ,  Won-Bong Jung

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L21/768 ,  H01L27/11521 ,  H01L29/423

CPC classification number: H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.