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1.发明申请公开(公告)号：US20180197719A1
公开(公告)日：2018-07-12
申请号：US15606025
申请日：2017-05-26
发明人： Yil-Hyung Lee , Yoo-Chul Kong , Jong-Kyu Kim , Seok-Woo Nam , Jong-Soon Park , Kyoung-Sub Shin
CPC分类号： H01J37/32412 , H01J37/32422 , H01J37/3435 , H01J37/3438 , H01J2237/083 , H01J2237/334
摘要： In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
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公开(公告)号：US10410839B2
公开(公告)日：2019-09-10
申请号：US15606025
申请日：2017-05-26
发明人： Yil-Hyung Lee , Yoo-Chul Kong , Jong-Kyu Kim , Seok-Woo Nam , Jong-Soon Park , Kyoung-Sub Shin
IPC分类号： H01L21/263 , H01J37/32 , H01J37/34
摘要： In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
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3.发明申请公开(公告)号：US20190272979A1
公开(公告)日：2019-09-05
申请号：US16413854
申请日：2019-05-16
发明人： Yil-Hyung Lee , Yoo-Chul Kong , Jong-Kyu Kim , Seok-Woo Nam , Jong-Soon Park , Kyoung-Sub Shin
摘要： In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
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公开(公告)号：US09997566B1
公开(公告)日：2018-06-12
申请号：US15602469
申请日：2017-05-23
发明人： Sang-Kuk Kim , Jong-Kyu Kim , Jong-Chul Park , Jong-Soon Park , Hye-Ji Yoon , Woo-Hyun Lee
IPC分类号： H01L43/12 , H01L27/22 , H01L43/02 , H01L43/08 , H01L29/423
CPC分类号： H01L27/228 , H01L27/222 , H01L29/4236 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.
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公开(公告)号：US20180158867A1
公开(公告)日：2018-06-07
申请号：US15602469
申请日：2017-05-23
发明人： Sang-Kuk KIM , Jong-Kyu Kim , Jong-Chul Park , Jong-Soon Park , Hye-Ji Yoon , Woo-Hyun Lee
CPC分类号： H01L27/228 , H01L27/222 , H01L29/4236 , H01L43/02 , H01L43/08 , H01L43/12
摘要： Manufacturing an MRAM device may include forming an upper electrode on a magnetic tunnel junction stack, where the stack may include a lower electrode layer, a magnetic tunnel junction layer and a middle electrode layer that are sequentially formed on an insulating interlayer and a lower electrode contact on a substrate. The upper electrode may be formed on the middle electrode layer. An upper electrode protective structure may be formed to cover at least a sidewall and an upper surface of the upper electrode. The middle electrode layer, the magnetic tunnel junction layer and the lower electrode may be patterned by an etching process to form a middle electrode, a magnetic tunnel junction pattern and a lower electrode, respectively. The upper electrode protective structure may isolate the upper electrode from exposure during the patterning, and the upper electrode protective structure may remain on the upper electrode subsequently to the patterning.
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